DRAM Address Mapping Table Error Correction via Segmentation
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Solution Overview
Problem
Current semiconductor memory systems face challenges in quickly performing error detection and correction on the address mapping table for nonvolatile memory devices, which is crucial for reliable data access and storage, especially as the size of the address mapping table increases with the capacity of the nonvolatile memory device.
Innovation Solution
A memory system that utilizes a dynamic random access memory (DRAM) to store the address mapping table, divided into units of address mapping data, and includes a controller to perform error detection and correction on target address mapping data, using a parity mechanism to correct errors and ensure accurate address translations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the address mapping table is stored in DRAM for nonvolatile memory devices, then the access speed is improved, but the error detection and correction time increases as the table size grows
Solution Approach 1:
The address mapping table is divided into multiple segments, each stored in a separate DRAM bank. This segmentation allows parallel access to different segments, maintaining high access speed while enabling independent error correction on smaller segments, thus reducing overall error correction time.
Solution Approach 2:
Parity information is pre-calculated and stored alongside the address mapping data in the DRAM. This preliminary preparation of error detection codes enables immediate error detection and correction without requiring additional computation time during access operations, even as the table size increases.
2Quantity of substance
If the address mapping table size increases to support high-capacity nonvolatile memory, then the storage capacity is improved, but the error detection and correction complexity increases
Solution Approach 1:
The large address mapping table is divided into smaller manageable segments stored in separate DRAM banks. Each segment can be independently accessed and corrected, reducing the complexity of error detection and correction operations while supporting high-capacity storage through the aggregated capacity of multiple segments.
Solution Approach 2:
Different DRAM banks storing segments of the address mapping table can be configured with optimized error correction parameters suitable for their specific characteristics. This local optimization reduces overall system complexity while maintaining high storage capacity support.
Data Source
AI summary
A memory system includes a nonvolatile memory device, a dynamic random access memory (DRAM) configured to store an address mapping table for an access to the nonvolatile memory device, and a controller configured to store, in the DRAM, the address mapping table that is divided in units of address mapping data, each of the units having a size of an interface of the DRAM, read, from the stored address mapping table, target address mapping data corresponding to a logical address that is received from a host, the target address mapping data including a target parity and physical addresses of the nonvolatile memory device, and perform an error correction on the read target address mapping data, using the target parity.