Mapping Table Loading in Memory Storage Apparatus
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Solution Overview
Problem
The limited capacity of buffer memory in memory storage apparatuses using rewritable non-volatile memory modules leads to inefficient execution of read commands, resulting in performance deterioration due to the need to sequentially load and replace mapping information, which slows down data access and processing.
Innovation Solution
A mapping table loading method that pre-loads non-continuous mapping information to a buffer area when the memory module is busy, utilizing the waiting time to reduce command execution time and replace mapping information with data, thereby optimizing buffer memory usage and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If mapping information is loaded sequentially to the buffer memory, then the buffer memory capacity is preserved, but the read command execution time increases and performance deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-loading mapping information into the buffer memory before it is actually needed for read operations. The memory control circuit predicts which mapping information will be needed based on read command patterns and loads it in advance during idle periods or alongside data transfer operations, thereby eliminating waiting time during actual read executions without requiring additional buffer capacity.
2Productivity
If multiple parts of mapping information are loaded simultaneously to the buffer memory, then read command execution efficiency improves, but the limited buffer memory capacity is exceeded
Solution Approach 1:
The patent merges two operations: loading mapping information and transferring data between buffer areas. The memory control circuit combines these previously separate operations into a single coordinated process, allowing mapping information to be loaded into the data buffer area while data is simultaneously being transferred, thereby doubling the effective throughput without increasing buffer capacity.
Solution Approach 2:
The patent introduces a temporal dimension to buffer memory usage by utilizing idle time periods and overlapping operations. Instead of sequentially loading mapping information only when the buffer is available, the system loads mapping information during idle periods and alongside data transfer operations, effectively using time as an additional resource dimension to increase throughput without expanding buffer capacity.
3Adaptability or versatility
If the buffer memory is used to store both mapping information and data, then buffer memory utilization is optimized, but the complexity of buffer management increases
Solution Approach 1:
The patent segments the buffer memory into distinct functional areas: a mapping information buffer area and a data buffer area. This segmentation allows each area to be managed independently with dedicated control logic, reducing the overall management complexity while still achieving high utilization. The memory control circuit maintains separate tracking and management mechanisms for each segment, avoiding the need for complex dynamic allocation algorithms.
Data Source
AI summary
A mapping table loading method and a memory storage apparatus are provided. The method includes: receiving a plurality of first read commands comprising a plurality of first logical units; executing a first logical-physical mapping table pre-loading operation to read a plurality of mapping information corresponding to the first logical units in a logical-physical mapping table from a rewritable non-volatile memory module to a first buffer area of a buffer memory according to a first executing sequence of the first read commands if the first logical units are not continuous logical addresses; and reading data belonging to the first logical units from physical erasing units to the first buffer area according to the mapping information of the first logical units, and replacing the mapping information of the first logical units in the first buffer area by the data belonging to the first logical units.