Mapping Table Segmentation for Memory Bandwidth Optimization
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Solution Overview
Problem
The existing memory storage apparatuses face inefficiencies in usage and performance due to the repeated loading of large logical address-physical address mapping tables during random read operations, leading to bandwidth waste and performance deterioration.
Innovation Solution
The proposed solution involves a method where the memory control circuit unit loads either a sub-logical address-physical address mapping table of smaller capacity in a first operating mode or a logical address-physical address mapping table of larger capacity in a second operating mode, depending on usage history, to optimize data access and reduce bandwidth waste.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory management circuit loads the logical address-physical address mapping table of larger capacity into the buffer memory, then the data access completeness is improved, but the bandwidth consumption increases and performance deteriorates during random read operations
Solution Approach 1:
The patent divides the logical address-physical address mapping table into multiple sub-tables, each storing mapping information for a specific range of logical addresses. During random read operations, the system loads only the relevant sub-table into the buffer memory, reducing bandwidth consumption while maintaining complete data access capability.
2Reliability
If the memory management circuit loads the logical address-physical address mapping table of larger capacity into the buffer memory, then the data access completeness is improved, but the performance deteriorates during random read operations
Solution Approach 1:
The mapping table is segmented into sub-tables corresponding to different logical address ranges. This segmentation enables the system to load only the necessary sub-table into buffer memory for random read operations, reducing access time by avoiding the need to search through a large entire mapping table.
3Device complexity
If the memory management circuit uses a fixed size for managing the logical address-physical address mapping table, then the system simplicity is maintained, but the usage efficiency decreases during random read operations
Solution Approach 1:
The patent introduces a dynamic loading mechanism where the system automatically determines which sub-table to load into buffer memory based on the command type and logical address range. This dynamic approach maintains system simplicity at the high level while improving usage efficiency by loading only necessary mapping information.
4Adaptability or versatility
If the memory management circuit loads different logical address-physical address mapping tables multiple times during random read operations, then the data accessibility is maintained, but the bandwidth waste increases
Solution Approach 1:
By segmenting the mapping table into sub-tables, the system can access different data ranges by loading only the relevant sub-table, avoiding the bandwidth waste of repeatedly loading the entire large mapping table for each random read operation.
Solution Approach 2:
The system pre-divides the mapping table into manageable sub-tables that can be independently loaded into buffer memory. This preliminary organization allows efficient data accessibility while minimizing bandwidth consumption by loading only the necessary sub-tables.
Data Source
AI summary
A mapping table loading method, a memory control circuit unit and a memory storage apparatus are provided. The method includes: receiving a first command; loading a first sub-logical address-physical address mapping table corresponding to the first command if an operating mode of a non-volatile rewritable memory module is a first operating mode; and loading a first logical address-physical address mapping table corresponding to the first command if the operating mode of the non-volatile rewritable memory module is a second operating mode, wherein the first logical address-physical address mapping table includes the first sub-logical address-physical address mapping table.