March Controller for SRAM Scan Testing
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Solution Overview
Problem
Current memory testing methods, such as scan testing and memory built-in self-test (MBIST), face challenges in efficiently testing SRAMs due to timing differentials and the complexity of programming scan patterns across multiple SRAMs, leading to sub-optimal test results and increased costs.
Innovation Solution
A novel march controller with a march data store, select register, and data loader is introduced, enabling the execution of scan-based testing using a single scan pattern across multiple SRAMs without the need for extensive programming, facilitating faster and more cost-effective testing by simplifying the generation and application of complex march test patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan testing is used to test memory arrays, then test coverage can be achieved, but the testing speed is significantly lower than the intended operating speed of the integrated circuit
Solution Approach 1:
The patent pre-loads march test pattern data into an on-chip memory structure before actual testing begins. This preliminary action allows the test controller to retrieve and execute test patterns at full operating speed without external intervention, resolving the speed limitation of traditional scan testing while maintaining comprehensive test coverage.
2Speed
If memory built-in self-test (MBIST) is implemented, then testing can be performed at operating speed, but the controller complexity and programming requirements increase significantly
Solution Approach 1:
The patent implements a universal march controller that can execute multiple different march test patterns through a single standardized interface and control structure. The on-chip memory stores various test patterns that can be selected and executed without additional programming, providing MBIST functionality at operating speed while minimizing controller complexity through multi-functionality.
3Reliability
If extensive programming is performed to achieve high test coverage across multiple SRAMs, then test completeness improves, but test time and cost increase
Solution Approach 1:
The patent enables the testing system to automatically execute comprehensive march test patterns across multiple SRAM devices using pre-loaded data in on-chip memory. The system serves itself by having the controller retrieve and execute test patterns from internal memory without external programming intervention, achieving high test completeness while minimizing test time and cost.
Data Source
AI summary
Embodiments include novel approaches for scan-based device testing using a march controller. A march data store can have sets of march element data stored thereon, each defining a respective march element of a march test sequence. A march select register can select each stored set of march element data according to the predefined march test sequence, and a march data loader can iteratively and sequentially output each set of march element data selected by the march select register. A memory built-in self-test controller can generate, in response to receiving each set of march element data output by the march controller, test stimulus data corresponding to the received set of march element data. The test stimulus data can input to a scan chain of the integrated circuit under test, and response data can be captured from the scan chain and assessed to determine whether the integrated circuit passed the test.