Marching Memory Bit-Level Cells Eliminate Wiring Delays
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Solution Overview
Problem
Current computer systems face performance limitations due to memory access bottlenecks caused by wiring delays and capacitance issues between processors and main memory, leading to high energy consumption and reduced processing speeds.
Innovation Solution
The implementation of a marching memory system with bit-level cells that utilize transfer-transistors, reset-transistors, and capacitors to efficiently store and transfer data, eliminating the need for global wires and reducing signal delay and power consumption by synchronizing data transfer with the CPU's clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional memory systems use global wires to connect processors and main memory, then data can be accessed across the system, but wire length delays access time and stray capacitance causes additional delay and power consumption
Solution Approach 1:
The patent segments the global memory system into distributed memory units, each with local storage and transfer transistors. Data is divided into bits stored in individual cells within memory units, eliminating the need for long global wires. Each memory unit operates independently with local bit-line connections, reducing wire length and capacitance effects.
Solution Approach 2:
The patent transitions from a centralized hierarchical memory architecture to a distributed two-dimensional array of memory units. Memory units are arranged in rows and columns with local interconnections, changing the dimensional organization from vertical hierarchy to horizontal distribution, thereby reducing signal path lengths.
2Productivity
If vector processors are used to improve memory bandwidth utilization, then processing efficiency increases, but the memory bottleneck between units remains unavoidable
Solution Approach 1:
The patent merges storage and transfer functions into unified memory units that can simultaneously perform both operations. Each memory unit contains storage elements and transfer transistors that work together to eliminate the separation between storage and bandwidth management, allowing concurrent access without bottlenecks.
Solution Approach 2:
The patent implements dynamic control of memory unit operations through clock signals that synchronize data transfer across the array. The transfer transistors are dynamically activated to route data between adjacent memory units, enabling flexible and adaptive bandwidth utilization that responds to processing demands.
3Ease of operation
If processors and main memory are connected through cache memory and global buses, then data access is enabled, but the bottleneck limits performance and increases energy consumption
Solution Approach 1:
The patent extracts the bottlenecking cache and global bus components from the memory system, replacing them with directly connected memory units that interface with processors through localized connections. This extraction eliminates the energy-consuming intermediate stages while preserving data access capability.
Solution Approach 2:
Each memory unit is self-sufficient with its own storage elements and transfer control, eliminating the need for centralized cache management and global bus arbitration. Memory units autonomously manage their data and transfer operations, reducing the energy overhead of centralized control mechanisms.
Data Source
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AI summary
An array of bit-level cells adapted for a marching memory operating with a single clock signal supply line, in which a plurality of bit-level cells are arranged in a matrix so that a set of information of byte size or word size aligned in a column direction of the matrix are transferred synchronously with a clock signal supplied from the single clock signal supply line, step by step, toward an output side of the marching memory along a row direction of the matrix from an input side of the marching memory, each of the arrays of bit-level cells aligned in the row direction comprising: a first bit-level cell configured to store a signal charge; an inter-unit circuit, connected to an output terminal of the first bit-level cell; and a second bit-level cell connected to an output terminal of the inter-unit circuit, wherein the inter-unit circuit isolates a storage state of the signal charge, between the first and second bit-level cells.