Marching Memory System Eliminates Wiring Bottleneck
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Solution Overview
Problem
Conventional computer systems face memory bottlenecks due to wiring delays and power consumption issues between processors and main memory, limiting processing speed and efficiency.
Innovation Solution
The implementation of a marching main memory system where information is transferred synchronously with a clock signal through an array of memory units, eliminating the need for global wires and reducing time delays and power consumption by using bi-directional data transfer and positioning strategies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional wired memory access is used, then memory capacity can be large, but access speed is limited by wire delays and bottlenecks
Solution Approach 1:
The patent extracts and eliminates the global wiring infrastructure from the memory system. Instead of using traditional wired buses connecting processors to main memory, the invention uses a mesh network where each processing element has direct access to nearby memory elements, removing the central wiring bottleneck entirely
Solution Approach 2:
The memory system is segmented into distributed memory elements organized in a mesh structure, where each element is locally accessible. This segmentation eliminates the need for a single centralized memory bus and allows parallel access paths throughout the system
2Use of energy by moving object
If wired memory access is used, then memory can be addressed globally, but power consumption increases due to wire capacitance
Solution Approach 1:
The patent implements local quality by organizing memory and processing elements in a spatially distributed mesh where each element communicates only with its immediate neighbors. This local communication approach dramatically reduces the capacitance and power consumption compared to global wired access, while maintaining system-wide addressability through coordinated local steps
3Productivity
If cache memory is used to avoid memory accessing, then processing speed improves, but memory bottleneck still exists between cache and main memory
Solution Approach 1:
The patent merges the traditional separation between cache and main memory into a unified distributed memory structure. Processing elements can access both frequently used data (functionally equivalent to cache) and less frequently used data (functionally equivalent to main memory) through the same mesh network, eliminating the bottleneck between cache and main memory while maintaining high-speed access
Data Source
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AI summary
A computer system encompasses a processor (11) including a control unit (111) and an ALU (112) configured to execute arithmetic and logic operations synchronized with the clock signal, and a marching main memory (31), which embraces an array of memory units, configured to store information in each of memory units and to transfer synchronously with the clock signal, providing the processor (11) with the stored information actively and sequentially so that the ALU (112) can execute the arithmetic and logic operations with the stored information. The results of the processing in the ALU (112) are sent out to the marching main memory (31), but there is only one way of instructions flow from the marching main memory (31) to the processor.