Margin Voltage Reduces Bitline Disturb in Non-Volatile Memory
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Solution Overview
Problem
Non-volatile memory cells experience unintended changes in threshold voltage due to program disturbs, particularly bitline disturbs, which worsen with increasing erase/program cycles and temperature, and density advancements, affecting memory cell reliability.
Innovation Solution
The implementation of a margin voltage (VMARG) with a lower magnitude than conventional voltages is applied to deselected global wordlines during programming operations, reducing the gate-to-drain voltage across unselected memory cells and minimizing bitline disturbs by using dedicated or existing circuitry to generate VMARG, which can be programmable and adjusted in small steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional voltages are applied to global wordlines during programming operations, then programming efficiency is maintained, but bitline disturb increases significantly (up to 60 mV)
Solution Approach 1:
The patent applies a margin voltage (VMARG) with lower magnitude than conventional voltages to deselected global wordlines during programming operations. This parameter change in voltage magnitude reduces the gate-to-drain voltage across unselected memory cells, thereby minimizing bitline disturbs from 60 mV to less than 7 mV while maintaining programming efficiency in selected cells.
2Productivity
If memory cell density is increased to improve storage capacity, then productivity increases, but bitline disturb worsens due to scaling effects
Solution Approach 1:
The patent introduces a margin voltage regime that scales with technology node advancements. As memory cell dimensions scale down, the VMARG magnitude is adjusted to maintain appropriate voltage margins, ensuring that bitline disturb remains controlled even as density increases and cells become more susceptible to electrical interference.
3Duration of action of stationary object
If erase/program cycles are increased to improve data retention, then durability improves, but bitline disturb accumulates in deselected rows
Solution Approach 1:
The patent applies margin voltage to deselected global wordlines before and during programming operations in selected rows. This preliminary protective action prevents charge injection and threshold voltage shifts in unselected memory cells, counteracting the cumulative bitline disturb that would otherwise occur with repeated erase/program cycles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly reduces bitline disturb effects from about 60 mV to less than 7 mV, enhancing the reliability and stability of non-volatile memory cell programming across various operational conditions.
Implementation Method 1
A positive gate-to-substrate voltage causes electrons to tunnel from the channel to a charge-trapping dielectric layer raising a threshold voltage (VT) of the transistor
Data Source
AI summary
A non-volatile memory that includes a shared source line configuration and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array.