Marking Memory Cells for Secure Word Line Verification
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Solution Overview
Problem
Existing memory circuits face challenges in securely verifying that erase, write, and read operations are performed on the intended memory cells, especially when an attacker can manipulate these operations and the verification process itself.
Innovation Solution
Incorporating a memory circuit design with electrically programmable non-volatile marking memory cells and bit lines/source lines that define a non-changeable memory state, allowing marker bits to identify associated word lines through unique bit sequences, enabling secure verification of operations by reading marker bits alongside data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If address dependent data encryption is used to verify memory operations, then security against manipulation is improved, but not all relevant cases are covered and verification reliability is insufficient
Solution Approach 1:
The memory circuit is segmented into data memory cells and separate marking memory cells. Each word line has associated marking cells that store verification information independently from the data cells, allowing comprehensive verification of all memory operations including erase, write, and read operations on the intended word lines.
Solution Approach 2:
Marking memory cells serve as intermediary elements between the data memory cells and the verification process. These marking cells store identification information about the intended word line, acting as a mediator that enables reliable verification of whether operations were performed on the correct targets without interfering with the actual data storage.
2Reliability
If marking memory cells with non-changeable state are introduced to identify word lines, then security against manipulation is improved, but device complexity increases
Solution Approach 1:
The marking memory cells are merged with the existing memory array structure, sharing the same word lines and being integrated into the memory cell array. This combining approach allows the marking functionality to be added without requiring completely separate verification circuits, thereby limiting the increase in device complexity while still achieving improved security.
Solution Approach 2:
The marking memory cells are designed to serve multiple functions: storing word line identification information, enabling verification of erase operations, verifying write operations, and preventing unauthorized manipulation. This multi-functionality reduces the need for separate verification mechanisms, thereby limiting the overall device complexity increase.
Data Source
AI summary
A memory circuit includes electrically programmable memory cells arranged in a non-volatile memory cell array along rows and columns, word lines, each word line coupled with one or more memory cells, non-volatile marking memory cells, wherein at least one word line of the word lines is associated with one or more marking memory cells, and marking bit lines, each associated with marking memory cells, marking source lines, each associated with marking memory cells, wherein, for marking memory cells, a physical connection from an associated marking source line and/or from an associated marking bit line to the marking memory cells defines those marking memory cells to a non-changeable state, wherein the marking memory cells are configured to identify the associated word line of respective marking memory cells in the non-changeable memory state.