MASAR Column Architecture for Low-Energy Neural MAC Computation
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Solution Overview
Problem
Current machine learning and neural network models require significant memory and computational resources for large numbers of weights, leading to increased memory and energy costs due to the need for extensive data transfer and multiplication-accumulate operations in digital hardware implementations.
Innovation Solution
The implementation of a Multiply-Accumulate Successive Approximation (MASAR) column using a plurality of MASAR cells with multipliers, unit capacitors, and digital logic to perform digital multiplication and analog summation, enabling efficient MAC operations and reducing the need for analog-to-digital conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If digital hardware implementations are used for MAC operations, then computational power can be increased, but energy consumption and time costs increase significantly
Solution Approach 1:
The patent combines multiple MAC operations and ADC conversion into a single integrated circuit architecture. The MASAR column performs both MAC computations and successive approximation register ADC conversion using shared hardware resources, eliminating the need for separate analog-to-digital conversion stages and reducing overall energy consumption while maintaining computational power.
Solution Approach 2:
The integrated circuit is designed with multi-functional processing elements that can perform both MAC operations and ADC conversion. The same computational units are reused for different functions throughout the computation pipeline, reducing hardware redundancy and lowering energy consumption per operation.
2Measurement precision
If the number of weights and layers in neural networks is increased, then model accuracy improves, but memory requirements and data transfer costs increase
Solution Approach 1:
The patent integrates weight storage and computation functions within the same processing elements. Weights are stored locally in the MASAR column and used directly in MAC operations without requiring transfer to separate memory units, reducing memory bandwidth requirements and enabling larger models to be deployed with fewer external memory resources.
3Measurement precision
If separate ADC conversion stages are added for each MAC operation, then digital output precision is improved, but device complexity and energy consumption increase
Solution Approach 1:
The patent merges the ADC conversion function with the MAC computation by implementing successive approximation register ADC directly within the MASAR column. This integration allows multiple MAC results to be converted to digital format using a single shared ADC unit rather than requiring separate ADC stages for each operation, reducing device complexity while maintaining precision.
Solution Approach 2:
The SAR ADC conversion is performed continuously alongside the MAC computations in a pipelined manner. While MAC operations are being computed, the ADC conversion proceeds in parallel using the same hardware resources, ensuring that precision is maintained without adding sequential conversion stages that would increase complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces energy and time costs by allowing for parallel and serial multi-bit precision MAC computations, improving hardware efficiency for AI/ML applications by using the same processing elements for both MAC calculations and ADC conversion.
Implementation Method 1
a unit capacitor configured to store the result as analog charge
Implementation Method 2
digital logic configured to perform analog summation of the analog charge of the unit capacitors
Data Source
AI summary
A multiply-accumulate successive approximation (MASAR) column is provided. The MASAR column includes a plurality of MASAR cells, each including a multiplier configured to perform digital multiplication between an input activation received to an input and an operand to compute a result, and a unit capacitor configured to store the result as analog charge. The MASAR column further includes digital logic configured to perform analog summation of the analog charge of the unit capacitors of the plurality of MASAR cells to determine a digital output of the multiplication.