Two-Stage MASH Sigma-Delta Modulator for ADPLL Noise Reduction
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Solution Overview
Problem
All-digital phase locked loop systems face challenges in reducing noise and spurs generated by sigma-delta modulators, particularly due to limitations in sampling frequency and stability issues with higher-order modulators, which affect frequency resolution and phase noise power.
Innovation Solution
A two-stage MASH 1-1 sigma-delta modulator configuration with a dithering mechanism and parallelism in each stage to reduce noise and spurs, where the least significant bit of the control word is modulated, and a dithering value is introduced to stabilize the system, improving speed and stability by removing subtraction from the critical path and performing operations in parallel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the order of the sigma-delta modulator is increased to reduce noise and spurs, then frequency resolution is improved, but stability deteriorates
Solution Approach 1:
The patent divides a high-order sigma-delta modulator into multiple lower-order stages (e.g., two first-order stages or one first-order and one second-order stage). Each stage processes a portion of the quantization noise shaping, and their outputs are combined. This segmentation maintains the overall noise reduction benefit while improving stability, as each individual stage is easier to stabilize than a single high-order stage.
2Measurement precision
If the sampling frequency is increased to reduce noise and spurs, then frequency resolution is improved, but device complexity increases
Solution Approach 1:
The patent changes the order parameter of the sigma-delta modulator instead of changing the sampling frequency. By adjusting the modulator order and using multi-stage configurations, the system achieves improved frequency resolution and noise performance without increasing the sampling frequency, thereby avoiding the associated increase in device complexity.
3Measurement precision
If a dithering mechanism is added to reduce periodic spurs, then signal quality is improved, but device complexity increases
Solution Approach 1:
The patent applies dithering at a minimal level - adding a small random signal just sufficient to break up periodic spurs without excessive dithering that would add significant noise. This partial action approach achieves the benefit of spur reduction while minimizing the impact on signal quality and keeping the added complexity low.
4Speed
If parallelism is employed to improve speed, then processing speed is improved, but device complexity increases
Solution Approach 1:
The patent segments the sigma-delta modulator into parallel stages or parallel processing paths within stages. Each segment processes data independently and simultaneously, then results are combined. This segmentation enables parallelism that improves processing speed while keeping each individual segment relatively simple, thus managing overall device complexity.
Data Source
AI summary
An all-digital phase locked loop system for generating an oscillator output signal under control of a digital reference input. The system comprises a digitally controlled oscillator, a digital loop filter for generating a multiple bit digital control signal for the digitally controlled oscillator, a sigma-delta modulator for generating an additional 1-bit digital control signal for the digitally controlled oscillator, a digital divider dividing the oscillator output signal and providing a digital divided signal, and a digital adder with a first, additive input to which the digital reference input is applied and a second, subtractive input to which the digital divided signal is applied. The digital adder provides a digital output, the most significant bits of which are applied to an input of the digital loop filter and the least significant bits of which are applied to an input of the sigma-delta modulator. In the preferred embodiment, the sigma-delta modulator is of a two-stage MASH configuration.