Mask Alignment for IC Interconnects Using Spacer Pitch Multiplication
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Solution Overview
Problem
The challenge in integrated circuit fabrication is the limited ability to form features of varying sizes due to the minimum pitch constraints of photolithographic techniques, leading to potential shorts and misalignment issues between pitch-multiplied and non-pitch-multiplied features, which can cause malfunction in integrated circuits.
Innovation Solution
A method is developed to increase misalignment tolerances by forming interconnects with wider portions that contact narrower spacers, where the wider interconnects have one side collinear or inset from the spacer, and using photoresist layers below the height of mask features to limit diffusion and enhance rounding effects, thereby increasing the distance between features and reducing the risk of shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography is used to pattern features, then manufacturing capability is achieved, but minimum pitch constraints limit feature size reduction and cause misalignment issues
Solution Approach 1:
The patent divides the feature formation process into multiple stages: first forming placeholder structures, then adding spacer material to create spacers, and finally removing placeholders to leave freestanding spacers. This segmentation allows achieving smaller effective pitch than the photolithographic minimum by using the spacer deposition step to halve the original feature pitch.
Solution Approach 2:
The patent introduces placeholder structures as intermediary elements that facilitate the formation of smaller features. These placeholders serve as templates for spacer deposition and are subsequently removed, leaving the desired fine-pitch spacer features. The placeholders act as a mediator between the photolithographic process and the final fine-pitch structure.
2Manufacturing precision
If pitch multiplication is used to reduce feature size, then minimum pitch constraint is overcome, but misalignment between pitch-multiplied and non-pitch-multiplied features causes shorts
Solution Approach 1:
The patent applies different properties to different parts of the structure: interconnects are made wider than spacers, and the interconnect sidewalls are positioned collinear or inset from the spacer sides rather than centered. This local quality differentiation creates alignment margin that prevents shorts between pitch-multiplied and non-pitch-multiplied features.
3Ease of operation
If interconnects are aligned to contact spacers, then connectivity is achieved, but misalignment risk increases due to small margins
Solution Approach 1:
The patent creates an asymmetric alignment relationship where interconnects are wider than spacers, and the interconnect sidewalls are positioned collinear or inset from the spacer sides. This asymmetric geometry provides one-sided alignment margin that increases the tolerance for misalignment while maintaining reliable contact.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases the misalignment tolerances and reduces the risk of shorts between features of different sizes, enhancing the reliability and precision of integrated circuit formation by maximizing the distance between neighboring features and aligning them with larger margins of error.
Implementation Method 1
photolithography is commonly used to pattern features, such as conductive lines, on a substrate
Implementation Method 2
The spacer material is selectively removed from horizontal surfaces in a directional spacer etch
Implementation Method 3
The placeholders are selectively removed relative to the spacer material to form a plurality of spacer loops
Data Source
AI summary
Alignment tolerances between narrow mask lines, for forming interconnects in the array region of an integrated circuit, and wider mask lines, for forming interconnects in the periphery of the integrated circuit, are increased. The narrow mask lines are formed by pitch multiplication and the wider mask lines are formed by photolithography. The wider mask lines and are aligned so that one side of those lines is flush with or inset from a corresponding side of the narrow lines. Being wider, the opposite sides of the wider mask lines protrude beyond the corresponding opposite sides of the narrow mask lines. The wider mask lines are formed in negative photoresist having a height less than the height of the narrow mask lines. Advantageously, the narrow mask lines can prevent expansion of the mask lines in one direction, thus increasing alignment tolerances in that direction. In the other direction, use of photolithography and a shadowing effect caused by the relative heights of the photoresist and the narrow mask lines causes the wider mask lines to be formed with a rounded corner, thus increasing alignment tolerances in that direction by increasing the distance to a neighboring narrow mask line.