Mask Assembly for Integrated Fan-Out Package Fabrication
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Solution Overview
Problem
The semiconductor industry faces challenges in simplifying the fabrication process and reducing costs for integrated fan-out packages, which are crucial for heterogeneous integration and future package development due to complex manufacturing processes and high costs.
Innovation Solution
The process involves forming conductive pillars on a wafer, encapsulating them with a protection layer, and then using a redistribution circuit structure with multiple inter-dielectric and conductive layers to create a reliable and efficient integrated fan-out package, including the use of conductive through insulator vias and insulating encapsulation to protect and connect the components effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional fabrication processes are used for integrated fan-out packages, then manufacturing precision and reliability can be maintained, but the fabrication process becomes complex and costs increase
Solution Approach 1:
The fabrication process is divided into distinct stages: forming conductive pillars on the wafer, encapsulating them with protection layers, creating redistribution circuit structures with multiple inter-dielectric and conductive layers, and forming conductive through insulator vias. This segmentation allows each stage to be optimized independently while maintaining overall reliability.
Solution Approach 2:
Conductive pillars are formed and encapsulated with protection layers before the wafer is diced into individual chips. This preliminary action protects the conductive structures during subsequent processing steps and simplifies the overall fabrication流程 by preparing components in advance.
2Ease of manufacture
If traditional packaging methods are used, then manufacturing processes are simpler, but routability and reliability for heterogeneous integration are insufficient
Solution Approach 1:
The patent transitions from planar packaging to three-dimensional integrated fan-out packaging with multiple stacked layers of inter-dielectric and conductive layers. This dimensional expansion enables heterogeneous integration and improved routability while maintaining manufacturing feasibility through standardized fabrication processes.
Solution Approach 2:
The package structure employs nested layers where conductive pillars are encapsulated within protection layers, which are then integrated into redistribution circuit structures with multiple inter-dielectric and conductive layers. This nested architecture achieves complex functionality while using systematic fabrication steps.
3Device complexity
If component protection during dicing is not implemented, then fabrication process is simpler, but component reliability is compromised
Solution Approach 1:
Protection layers are formed over the conductive pillars before the wafer undergoes dicing. This preliminary protective action ensures that the conductive structures are shielded during the mechanical cutting process, preventing damage while maintaining relatively simple fabrication steps.
Data Source
AI summary
A first mask and a second mask are sequentially provided to perform a multi-step exposure and development processes. Through proper overlay design of the first mask and the second mask, conductive wirings having acceptable overlay offset are formed.