Mask Conversion Hardware for High-Order Secure Sharing
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Solution Overview
Problem
Conversions between arithmetic and Boolean masking operations are a significant performance bottleneck in secure implementations of cryptographic algorithms, particularly in post-quantum cryptography, and existing hardware solutions are either restricted to lower security orders or require a large number of gates and cycles.
Innovation Solution
A flexible hardware architecture is proposed that accelerates conversions between arithmetic and Boolean masking using optimized hardware converters, which can be instantiated at arbitrary security orders, requiring less area and cycles, and allows for trade-offs between area, latency, and throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing hardware solutions are used for mask conversions, then security order is limited to lower levels, but hardware area and cycle requirements increase
Solution Approach 1:
The conversion process is divided into multiple addition layers, where each layer processes a subset of shares. This segmentation allows the hardware to handle higher security orders by breaking down the complex conversion into manageable stages, reducing the instantaneous hardware area required while maintaining high security order support.
Solution Approach 2:
The hardware architecture uses dynamic resource allocation where the number of active adders and shares processed varies across different layers. This dynamic approach allows the same hardware to efficiently handle different security orders by activating only the necessary resources, optimizing the area-time tradeoff.
2Reliability
If existing hardware solutions are used for mask conversions, then security order is limited to lower levels, but conversion cycles increase
Solution Approach 1:
By segmenting the conversion into parallel addition layers, the hardware can process multiple share combinations simultaneously across different layers. This parallel segmentation reduces the total conversion cycles required while supporting higher security orders, as each layer operates independently and contributes to the final conversion result.
Solution Approach 2:
The hardware architecture maintains continuous operation across addition layers with pipelined processing, where outputs from one layer immediately feed into the next layer without idle cycles. This continuous useful action minimizes conversion cycles while handling complex high-order security conversions.
3Productivity
If more hardware resources are allocated for mask conversions, then throughput increases, but hardware area increases
Solution Approach 1:
The hardware converter is designed with universal adder units and share processing logic that can be dynamically configured for different throughput requirements. The same hardware blocks serve multiple functions across different addition layers and security orders, achieving high throughput without proportionally increasing hardware area through resource sharing and multi-functionality.
Solution Approach 2:
The architecture dynamically adjusts the number of active processing units and parallel streams based on throughput requirements. This dynamic configurability allows the system to scale throughput by activating additional hardware resources only when needed, rather than maintaining fixed high-throughput hardware that would consume excessive area during lower throughput operations.
Data Source
AI summary
A hardware converter configured to convert d arithmetic shares of x to d Boolean shares of x. The hardware converter has a plurality of addition layers in a tree structure. Each layer has a plurality of secure bit adders.