Mask Conversion Circuit Using Parallel XOR-AND Units
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Solution Overview
Problem
Conventional circuits for converting Boolean and arithmetic masks are inefficient due to a high number of logic gates and slow operating speeds, making them vulnerable to side-channel crypto-analyses like differential power attacks.
Innovation Solution
A circuit and method utilizing multiple converting units that perform XOR and AND operations on input data bits to reduce the number of logic gates and enhance processing speed, specifically designed to convert Boolean masks into arithmetic masks and vice versa, with a focus on reducing the overall complexity and increasing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional circuits are used for converting Boolean and arithmetic masks, then the conversion function is achieved, but the number of logic gates is large and operating speed is slow
Solution Approach 1:
The converting circuit is divided into multiple converting units (first converting unit, second converting unit, third converting unit, etc.), where each unit processes specific bits of the mask. For example, the first converting unit processes the first bit, the second converting unit processes the second bit, and so on. This segmentation reduces the complexity of each individual unit and enables parallel processing, thereby improving operating speed while reducing overall logic gate count.
Solution Approach 2:
The patent transforms the mask conversion problem from a sequential processing approach to a parallel processing approach by introducing multiple converting units that operate simultaneously on different bits. This dimensional change from time-sequential to space-parallel processing significantly improves operating speed while the modular structure keeps each unit's logic gate count manageable.
2Device complexity
If conventional circuits are used for converting Boolean and arithmetic masks, then the conversion function is achieved, but the overall number of logic gates is high
Solution Approach 1:
By segmenting the converting circuit into multiple specialized units, each handling specific bit positions, the patent achieves both reduced complexity per unit and improved overall efficiency. Each converting unit is optimized for its specific function, reducing redundant logic gates while maintaining high conversion throughput through parallel operation.
Solution Approach 2:
Each converting unit is designed to handle multiple operations (XOR, AND, NOT) within a unified structure, making the circuit multi-functional. This universality allows the same basic unit structure to be replicated across multiple bit positions, reducing overall design complexity while maintaining high conversion efficiency through parallel execution.
Data Source
AI summary
A circuit for converting Boolean and arithmetic masks includes “m” converting units, wherein m is an integer greater than 1. Each of the m converting unit includes; a first converting unit configured to receive first bits of input data, output one of the first bits as a first output bit, perform an XOR operation with respect to at least part of the first bits, and output an XOR operation result as a first intermediate result bit to a next converting unit in a sequence of converting unit ranging between 2 and n−1th; and an nth converting unit, wherein n is an integer greater than or equal to 2 and less than or equal to m, configured to receive n−1th bits and nth bits of the input data, and at least one of an n−1th intermediate result bit and n−1th output bit from an n−1th converting unit, perform an AND operation and the XOR operation with respect to a first group of the received bits, output an operation result for the first group as an nth output bit, perform the AND operation and the XOR operation with respect to a second group of the received bits, and output an operation result of the second group as an nth intermediate result bit.