Multi-patterning Mask Decomposition for Parasitic RC Optimization
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Solution Overview
Problem
In semiconductor integrated circuit fabrication, multi-patterning methods like SADP and MPMS result in patterns with different width biases between first and second masks, leading to inaccurate parasitic capacitance and resistance simulations if not properly accounted for, affecting IC design and performance.
Innovation Solution
A method and tool for assessing parasitic capacitive couplings by decomposing layouts into groups assigned to appropriate masks using a specially programmed processor, computing RC impact cost functions to optimize capacitance, resistance, or RC couplings, and assigning patterns to masks based on these calculations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multi-patterning methods (SADP, MPMS) are used to achieve smaller pitch patterns, then manufacturing capability at advanced nodes is improved, but parasitic capacitance and resistance simulations become inaccurate due to different width biases between masks
Solution Approach 1:
The patent applies local quality by recognizing that different mask assignments produce different line width biases and parasitic effects at different locations in the layout. The system evaluates specific spacing relationships (dense-dense, dense-iso, iso-iso) and assigns masks locally to minimize parasitic capacitance and resistance, rather than using a uniform mask assignment approach.
Solution Approach 2:
The patent changes the parameter of mask assignment based on spacing relationships between patterns. By computing RC impact cost functions for different mask assignments and selecting the optimal assignment, the system adjusts mask parameters to achieve accurate parasitic capacitance and resistance simulations while maintaining the benefits of multi-patterning for small pitch fabrication.
2Area of stationary object
If multi-patterning methods are used to reduce overall IC layout size, then device density is improved, but simulation accuracy of electrical characteristics deteriorates
Solution Approach 1:
The patent segments the layout into different regions based on spacing relationships between patterns. By dividing the layout into dense-dense, dense-iso, and iso-iso regions, the system can apply appropriate mask assignments to each segment, maintaining both compact layout and accurate electrical simulation.
Solution Approach 2:
The patent performs preliminary analysis of spacing relationships and computes RC impact cost functions before finalizing mask assignments. This preliminary action allows the system to predict and optimize electrical characteristics before fabrication, ensuring both layout compactness and simulation accuracy.
Data Source
AI summary
A portion of a layout of a single layer of an integrated circuit is to be multi-patterned. The patterns are divided into first and second groups, to be patterned on the single layer by a first mask or a second mask. For each portion of each pattern, a spacing relationship is determined between that portion and any adjacent pattern on either or both sides. A processor computes a first capacitance (C), resistance (R), or resistance-capacitance (RC) cost of assigning the first group to the first mask and the second group to the second mask, and a second cost of assigning the first group to the second mask and the second group to the first mask, based on the spacing relationships. The first group is assigned to the first mask and the second group to the second mask if the first cost is lower than the second cost.