Mask-Defined ROM Bit Formation Without Peripheral Redesign
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Solution Overview
Problem
Existing semiconductor ROM technologies require redesigning peripheral circuitry, leading to long and costly product development, low yield, and extended test times, with no straightforward method to transform EPROM topologies into mask-programmable memory without altering the fabrication process.
Innovation Solution
A method to transform CMOS-compatible single-poly one-time programming (OTP) memory into coded non-volatile memory by forming specific polysilicon gates and diffusion regions, with block or floating polysilicon layers, allowing for the creation of mask-defined ROM bits that distinguish bit polarity through open circuits and resistors without altering the existing fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If EPROM topologies are transformed into mask-programmable memory by redesigning peripheral circuitry, then memory functionality is improved, but development time and cost increase
Solution Approach 1:
The patent applies preliminary action by pre-configuring the peripheral circuitry to be compatible with both EPROM and mask-programmable memory functionalities. The circuit design is prepared in advance to accept different memory types without requiring redesign, thus enabling transformation while avoiding development time delays.
Solution Approach 2:
The patent implements universality by designing peripheral circuitry that can serve multiple memory types. The same circuit architecture supports both EPROM and mask-programmable memory operations, allowing the system to adapt to different memory functionalities without requiring separate dedicated circuits for each type.
2Adaptability or versatility
If EPROM topologies are transformed into mask-programmable memory by redesigning peripheral circuitry, then memory functionality is improved, but development cost increases
Solution Approach 1:
The patent reduces development cost by creating universal peripheral circuitry that can manufacture both EPROM and mask-programmable memory devices using the same production line and tooling. This multi-functional approach eliminates the need for separate manufacturing setups, thereby reducing overall development and production costs.
Solution Approach 2:
The patent utilizes parameter changes to transform existing EPROM circuitry into mask-programmable memory circuits by modifying operational parameters rather than physical structure. This allows the same hardware to be reconfigured for different memory types through changes in voltage, timing, or control signals, avoiding costly physical redesigns.
3Adaptability or versatility
If existing fabrication processes are altered to create mask-defined ROM bits, then memory transformation is achieved, but process complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-establishing mask-defined regions and contact structures during the standard fabrication process. These preliminary structures are configured to automatically form the desired ROM bit patterns without requiring additional complex processing steps, thus achieving memory transformation while maintaining process simplicity.
Solution Approach 2:
The patent merges the formation of mask-defined ROM bits with the existing fabrication process steps. By combining the creation of diffusion regions, contacts, and gate structures into the standard manufacturing sequence, the patent achieves memory transformation without adding separate complex fabrication stages.
4Adaptability or versatility
If peripheral circuitry is redesigned for mask-programmable memory, then memory functionality is improved, but test time increases
Solution Approach 1:
The patent reduces test time by implementing universal test protocols that can verify both EPROM and mask-programmable memory functionalities using the same test equipment and procedures. The peripheral circuitry is designed to present a unified interface that simplifies testing, allowing comprehensive validation without requiring separate extensive test sequences for different memory types.
Data Source
AI summary
A mask-defined read-only memory array is formed on a substrate, and includes a first ROM bit and a second ROM bit of opposite polarities. The first ROM bit has a first MOS transistor and a first block layer formed over a first region of the substrate. A second source/drain region of the first MOS transistor and a first diffusion region are formed in a first region of the substrate on opposite sides of the first block layer. The second ROM bit includes a second MOS transistor.


