Mask Design for Embedded Memory Gate Dielectric
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Solution Overview
Problem
The integration of embedded memory in integrated circuits (ICs) faces challenges due to residue defects introduced during the patterning and removal of oxide layers, which lead to contamination and defects, affecting the manufacturing yield.
Innovation Solution
The method involves removing the first, second, and third oxide layers from the fifth logic sub-region prior to the nitrogen plasma treatment and annealing process, and selectively removing the fourth oxide layer after these processes, thereby reducing residue defects and improving leakage performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all oxide layers are treated with nitrogen plasma and annealing processes, then gate dielectric quality is improved, but residue defects and contamination increase
Solution Approach 1:
The patent segments the oxide layers into two groups: the first three oxide layers are removed before plasma treatment, while the fourth oxide layer remains for treatment. This segmentation allows selective application of nitrogen plasma and annealing processes, improving gate dielectric quality at the treated interface without generating residues from treating all oxide layers
Solution Approach 2:
The patent extracts and removes the first three oxide layers from the structure before applying nitrogen plasma treatment. By taking out these layers that would generate harmful residues, the process maintains the benefits of plasma treatment on the remaining fourth oxide layer while eliminating the source of contamination and residue defects
2Reliability
If multiple oxide layers are removed and treated, then leakage performance is improved, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into distinct phases: removal of the first three oxide layers, followed by selective treatment of the fourth oxide layer with nitrogen plasma and annealing. This segmentation simplifies the overall process by avoiding the complexity of treating all oxide layers uniformly, while still achieving improved leakage performance through targeted treatment of the critical fourth layer
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces residue defects and contamination, enhancing the manufacturing yield by minimizing the treatment and removal of gate dielectric precursor material, leading to improved IC performance.
Implementation Method 1
nitrogen plasma treatment and annealing process
Implementation Method 2
nitrogen plasma treatment and annealing process
Data Source
AI summary
Various embodiments of the present application are directed to a method for forming an integrated circuit (IC), and the associated integrated circuit. In some embodiments, a substrate is provided including a logic region having a plurality of logic sub-regions including a low-voltage logic sub-region and a high-voltage logic sub-region. The method further comprises forming a stack of gate dielectric precursor layers on the plurality of logic sub-regions and removing the stack of gate dielectric precursor layers from the low-voltage logic sub-region and the high-voltage logic sub-region. The method further comprises forming a high-voltage gate dielectric precursor layer on the low-voltage logic sub-region and the high-voltage logic sub-region and removing the high-voltage gate dielectric precursor layer from the low-voltage logic sub-region. The low-voltage logic sub-region has a logic device configured to operate at a voltage smaller than that of another logic device of the high-voltage logic sub-region.