Individual Mask Error Model for Lithography Verification
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Solution Overview
Problem
Current mask verification methods in optical lithography struggle to accurately predict patterning performance due to systematic errors in mask manufacturing, leading to unpredictable device yields and inefficiencies in process optimization, as they primarily focus on detecting isolated point defects rather than systematic errors that affect process windows and design defects.
Innovation Solution
The development of an individual mask error model that extracts physical mask data from inspection data, generates systematic mask error parameters, and predicts patterning performance, allowing for proactive qualification and optimization of masks before wafer exposure, using a combination of mask inspection tools and model-based data analysis systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional mask verification methods focusing on point defect detection are used, then isolated defects can be identified, but systematic mask errors affecting patterning performance and device yields cannot be accurately predicted
Solution Approach 1:
The patent transforms mask verification from simple defect presence/absence detection to quantitative measurement of systematic error parameters (CD variations, line edge roughness, pattern placement accuracy). By changing the measurement parameters from binary defect detection to continuous physical quantity measurement, the system can now predict patterning performance and device yields accurately.
Solution Approach 2:
The patent replaces traditional optical inspection systems with a computational modeling system that uses physics-based lithography simulation. Instead of relying on optical detection limitations, the system substitutes mechanical/optical measurement with computational prediction using process models that simulate the actual lithography printing process, enabling accurate prediction of systematic errors.
2Manufacturing precision
If extensive OPC and RET techniques are applied to achieve low-k1 lithography, then patterning capability is improved, but mask complexity and verification difficulty increase dramatically
Solution Approach 1:
The patent implements a feedback loop where the computational verification system analyzes the actual mask physical properties and compares them against the intended design pattern. The system provides feedback information about systematic deviations, enabling iterative optimization of both mask manufacturing processes and OPC designs to achieve the desired low-k1 patterning performance.
Solution Approach 2:
The patent performs comprehensive mask verification and prediction of patterning performance before actual wafer fabrication. By conducting computational simulations and analyzing systematic errors in advance, the system identifies potential issues with complex OPC patterns and mask manufacturing variations before they result in costly wafer scrap, enabling proactive process optimization.
3Productivity
If mask manufacturing systematic errors are not accounted for, then manufacturing process is simple, but device yields become unpredictable and process optimization is inefficient
Solution Approach 1:
The patent enables the mask verification system to automatically characterize its own measurement system and extract physical mask properties from inspection data. The computational model self-calibrates by comparing measured mask features with design specifications, automatically generating accurate predictions of patterning performance without requiring manual intervention or external calibration standards.
Data Source
AI summary
Methods and systems are disclosed to inspect a manufactured lithographic mask, to extract physical mask data from mask inspection data, to determine systematic mask error data based on differences between the physical mask data and mask layout data, to generate systematic mask error parameters based on the systematic mask error data, to create an individual mask error model with systematic mask error parameters, to predict patterning performance of the lithographic process using a particular mask and/or a particular projection system, and to predict process corrections that optimize patterning performance and thus the final device yield.