Mask Layer for FinFET Metal Gate Cutting
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing the loss of inter-layer dielectric (ILD) layers during the fabrication of FinFET devices, which can lead to damage to the epitaxial source/drain regions and affect the overall device performance.
Innovation Solution
A method is introduced that involves forming a mask layer with a slower etch rate than the metal gate structure, allowing for reduced ILD loss during the metal gate cutting process, and using a bi-layered or single-layered mask structure to protect the ILD, thereby minimizing damage to the epitaxial source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a fast etch process is used to remove the metal gate structure, then the manufacturing efficiency is improved, but the inter-layer dielectric layer is damaged and lost
Solution Approach 1:
A mask layer is introduced as an intermediary between the etch process and the ILD layer. This mask layer has an etch rate that is at least twice as fast as the ILD layer, allowing it to be selectively removed while protecting the ILD layer from damage. The mask layer absorbs the harsh etching conditions, preventing direct damage to the underlying ILD layer while still enabling efficient metal gate structure removal.
Solution Approach 2:
The solution changes the etch rate parameter by selecting a mask layer material with significantly different etch characteristics compared to the ILD layer. By choosing a material that etches at least twice as fast, the process enables aggressive etching of the metal gate structure without proportionally damaging the ILD layer, thus resolving the contradiction between etch speed and ILD layer integrity.
2Manufacturing precision
If the etch rate of the mask layer is increased to protect the ILD layer, then the ILD layer loss is reduced, but the etching process time is extended
Solution Approach 1:
Instead of slowing down the etch process to protect the ILD layer, the solution changes the material parameter by selecting a mask layer with high etch rate. This allows the etch process to proceed quickly through the mask layer while the ILD layer remains protected due to its slower etch rate, thus maintaining both speed and protection.
Solution Approach 2:
The structure uses a composite approach with multiple layers having different etch rates. The mask layer material is specifically chosen to have at least twice the etch rate of the ILD layer, creating a composite structure where the top layer sacrifices itself quickly while protecting the underlying sensitive layer, optimizing both process time and protection.
3Device complexity
If a single-layer mask structure is used, then the device complexity is reduced, but the protection effectiveness against ILD layer loss is insufficient
Solution Approach 1:
The mask structure uses a composite of multiple layers with different materials and etch rates. The first mask layer has an etch rate at least twice that of the ILD layer, while the second mask layer has a slower etch rate. This composite structure provides graduated protection, allowing the etch process to proceed efficiently while reliably protecting the ILD layer from excessive loss.
Solution Approach 2:
The mask structure is segmented into multiple layers with different functional characteristics. The first mask layer is optimized for fast etching to remove the metal gate structure, while the second mask layer provides slower etching for refined protection of the ILD layer. This segmentation allows each layer to perform its specific function optimally, enhancing overall protection reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the loss of the first ILD layer during the metal gate cutting process, preventing damage to the epitaxial source/drain regions and improving the reliability of the FinFET device fabrication.
Implementation Method 1
forming a mask layer with a slower etch rate than the metal gate structure, allowing for reduced ILD loss during the metal gate cutting process
Data Source
AI summary
A method includes forming a metal gate structure over a first fin, where the metal gate structure is surrounded by a first dielectric material, and forming a capping layer over the first dielectric material, where an etch selectivity between the metal gate structure and the capping layer is over a pre-determined threshold. The method also includes forming a patterned hard mask layer over the first fin and the first dielectric material, where an opening of the patterned hard mask layer exposes a portion of the metal gate structure and a portion of the capping layer. The method further includes removing the portion of the metal gate structure exposed by the opening of the patterned hard mask layer.