Mask Layout Dummy Patterns for CMP Dishing Control
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Solution Overview
Problem
The dishing phenomenon occurs during the chemical mechanical polishing (CMP) process for copper metal wires, leading to increased sheet resistance and reliability issues in semiconductor devices due to the higher polishing rate of copper compared to insulation layers, causing excessive removal and groove formation.
Innovation Solution
A mask layout design that divides the wiring region into first and second regions with strategically placed dummy patterns, including first and second dummy regions, to adjust the polishing rate and prevent excessive removal, specifically arranging contact regions in a matrix shape and second dummy regions in stripe or L-shapes to minimize dishing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper is used for metal wire formation, then electrical resistivity is reduced and electromigration resistance is improved, but the copper layer is easily oxidized and chemical reactions with etching chemicals are complex
Solution Approach 1:
A barrier layer is introduced as an intermediary between the copper layer and the etching chemicals. This barrier layer prevents direct contact between copper and etching chemicals, eliminating the complex chemical reactions and oxidation issues while maintaining copper's excellent electrical and electromigration properties.
2Manufacturing precision
If the copper layer is planarized by CMP process, then the metal wire is formed, but the copper layer develops dishing phenomenon with grooves due to higher polishing rate
Solution Approach 1:
Dummy patterns are strategically placed in specific regions (first dummy patterns in first regions, second dummy patterns in second regions) to create local variations in polishing behavior. These dummy patterns have different polishing rates than the copper layer, allowing control over the local polishing process to prevent dishing in critical areas while maintaining overall planarization.
3Productivity
If the width of metal wiring becomes greater, then the dishing phenomenon occurs more severely, but reducing wire width limits current carrying capacity
Solution Approach 1:
The wiring region is divided into different regions with different dummy pattern configurations. First dummy patterns are placed in first regions and second dummy patterns in second regions, creating localized polishing control that prevents dishing in wider wiring areas without requiring reduction of overall wire width, thus maintaining current carrying capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed mask layout effectively suppresses the dishing phenomenon, maintaining the integrity of metal wires and reducing sheet resistance, thereby enhancing the reliability and performance of semiconductor devices.
Implementation Method 1
the copper layer is planarized by a chemical mechanical polishing (CMP) process
Data Source
AI summary
In a method of designing a mask layout, a wiring region for forming a metal wire is established, the wiring region having at least a standard width. Contact regions for forming contacts electrically connected to the metal wire are established in the wiring region. The contact regions adjacent to each other are grouped to divide the wiring region into a first region and a second region including the contact regions. First dummy regions are established in the first region, the first dummy regions corresponding to regions for forming first dummy patterns. Second dummy regions are established among the contact regions in the second region, the second dummy regions corresponding to regions for forming second dummy patterns.