Lithographic Mask Layout Synthesis for Faster OPC-ILT Correction

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Solution Overview

Problem

The existing methods for correcting mask layouts in semiconductor manufacturing are time-consuming due to the iterative nature of optical proximity correction (OPC) and inverse lithographic technology (ILT) processes, which require multiple iterations to produce defect-free IC layouts on wafers.

Innovation Solution

A convolutional neural network is trained offline with a database of corrected and enhanced mask layouts and their corresponding IC layouts to predict defect-free projections, reducing the need for time-consuming simulations and iterations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If iterative OPC and ILT processes are used to correct mask layouts, then manufacturing precision of IC layouts is improved, but productivity deteriorates due to time-consuming simulations and multiple iterations

Engineering Contradiction:

Improvedefect-free IC layoutVSAvoidmask correction time

Core Design Contradiction:

Manufacturing precisionVSProductivity

Solution Approach 1:

A database of pre-computed corrected and enhanced mask layouts is created before actual production use. This database contains pre-calculated results from iterative OPC and ILT processes, allowing rapid retrieval without repeating time-consuming simulations during actual mask correction operations

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Instead of performing repeated iterative corrections, the patent uses a database containing copied pre-computed correction results. The system retrieves appropriate corrections from the database based on layout characteristics, avoiding the need to re-execute lengthy simulation and iteration processes

Inventive Principle:

Principle #26Copying

2Manufacturing precision

If multiple iterations of mask layout modification and projection simulation are performed, then manufacturing precision is improved, but loss of time increases significantly

Engineering Contradiction:

ImproveIC layout qualityVSAvoiditeration time

Core Design Contradiction:

Manufacturing precisionVSLoss of time

Solution Approach 1:

The database is prepared in advance by performing all necessary iterative modifications and projection simulations. This preliminary computation stores the relationship between various mask layouts and their corresponding defect-free IC layout outcomes, eliminating the need for repeated time-consuming iterations during actual production

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent creates a repository of copied correction patterns and outcomes from previous iterations. These pre-computed results are stored and reused, replacing the need to re-perform lengthy simulation cycles for each new mask layout correction task

Inventive Principle:

Principle #26Copying

Data Source

PatentUS12566384B2Method for mask data synthesis with wafer target adjustment

Publication Date: 2026.03.03 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method for manufacturing a lithographic mask for an integrated circuit includes performing an optical proximity correction (OPC) process to an integrated circuit mask layout to produce a corrected mask layout. The method further includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout. The method also includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout.