Semiconductor Mask Layout With Silicide Blocking for EOS Resistance
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Solution Overview
Problem
Electrical Overstress (EOS) related failures occur in the silicide region of Extended Drain MOS (EDMOS) devices used in level shifter circuits, leading to damage and malfunction due to excessive current migration.
Innovation Solution
A mask layout is designed to include a silicide blocking region that overlaps the gate electrode and source/drain regions, forming a silicide blocking film to prevent current flow towards the source region during EOS events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a silicide region is formed on the source region to reduce resistance and help current flow, then electrical conductivity is improved, but the device becomes susceptible to EOS failures due to current migration
Solution Approach 1:
The source region is divided into two distinct zones: a silicide region and a silicide blocking region. The silicide region provides low resistance for normal operation, while the silicide blocking region (formed by depositing an insulating film such as silicon oxide or silicon nitride) prevents current migration during EOS events. This segmentation allows the source region to simultaneously achieve high conductivity and EOS resistance.
Solution Approach 2:
Different portions of the source region are given different properties: the silicide region has high electrical conductivity for normal current flow, while the silicide blocking region has insulating properties to prevent current migration. By applying local quality differentiation, the device achieves both low resistance operation and protection against EOS failures.
2Power
If the gate-source resistance is reduced by forming silicide on the source region, then device performance is improved, but the device becomes more vulnerable to EOS stress
Solution Approach 1:
The source region is segmented into a silicide portion and a silicide blocking portion. The silicide portion reduces gate-source resistance for improved power efficiency, while the silicide blocking portion (with insulating film) prevents EOS stress from propagating to the source region, thus resolving the contradiction between low resistance and EOS vulnerability.
3Ease of operation
If current flow toward the source region is allowed during EOS events, then normal device operation is maintained, but EOS-related failures occur due to excessive current
Solution Approach 1:
The silicide blocking region is formed in advance during manufacturing by depositing an insulating film on a portion of the source region. This preliminary protective structure is already in place before EOS events occur, preventing current migration and EOS failures without affecting normal device operation.
Solution Approach 2:
The silicide blocking region acts as an intermediary barrier between the gate electrode and the source region. During EOS events, this intermediate insulating structure prevents excessive current from reaching the source region, thereby protecting the device while allowing normal operation to proceed uninterrupted.
Data Source
AI summary
A mask layout for forming a semiconductor device includes an active mask pattern, a gate electrode mask pattern, a silicide blocking mask pattern, and a contact mask pattern. The active mask pattern forms source and drain regions in a substrate. The gate electrode mask pattern, disposed to overlap the active mask pattern, forms a gate electrode between the source region and the drain region. The silicide blocking mask pattern is disposed to overlap the gate electrode mask pattern and the active mask pattern in the gate electrode, the source region, and the drain regions to form a silicide blocking region. The contact mask pattern, disposed spaced apart from the silicide blocking mask pattern, forms a contact plug on the substrate. The silicide blocking mask pattern covers the gate electrode mask pattern and extends to the active mask pattern.