Mask Layout Design for Crack Resistance via Stress Simulation
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Solution Overview
Problem
Current mask layout design methods in semiconductor manufacturing fail to effectively detect and mitigate stress weak points, leading to cracks and warpage in semiconductor devices, which complicates the manufacturing process and reduces the reliability of integrated circuits.
Innovation Solution
A method that involves designing a full-chip layout, extracting representative patterns, detecting stress weak points using finite element method (FEM) simulations, verifying these points by forming patterns on a wafer, and changing design rules through shape optimization to minimize stress and prevent cracks, thereby enhancing the robustness of the mask layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional mask layout design methods are used, then the manufacturing process is simple, but stress weak points are not detected leading to cracks and warpage
Solution Approach 1:
The patent applies preliminary action by performing stress simulation and detecting stress weak points during the mask layout design phase, before actual mask manufacturing. This allows potential crack locations to be identified and addressed in advance through layout modification, preventing cracks and warpage in the final semiconductor devices without adding complexity to the manufacturing process.
Solution Approach 2:
The patent segments the full-chip layout into representative patterns for stress simulation analysis. By dividing the complex full-chip layout into manageable representative patterns, the system can efficiently detect stress weak points through FEM simulation and apply targeted layout modifications to specific problematic areas, improving crack resistance without requiring complete redesign of the entire chip layout.
2Measurement precision
If stress simulation is performed on full-chip layout, then stress detection accuracy is improved, but processing time increases
Solution Approach 1:
The patent extracts representative patterns from the full-chip layout to perform stress simulation. Instead of simulating the entire complex full-chip layout, the system identifies and extracts key representative patterns that capture the essential stress characteristics. This extraction approach maintains high stress detection accuracy while significantly reducing processing time by focusing computational resources on critical areas only.
3Reliability
If design rules are modified to reduce stress, then crack resistance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements feedback by using stress simulation results to guide layout modifications. The stress weak points detected through FEM simulation provide feedback information that directs where and how to modify the layout design rules. This feedback loop ensures that layout modifications are precisely targeted at stress-prone areas, improving crack resistance while maintaining manufacturing precision by avoiding unnecessary modifications in low-stress regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly accelerates stress weak point detection and minimizes stress in the mask layout, resulting in a crack-resistant design that improves the reliability of both masks and semiconductor devices by optimizing the layout to prevent damage.
Implementation Method 1
detecting a stress weak point based on a stress simulation using a finite element method (FEM) with respect to the representative pattern
Data Source
AI summary
A mask layout design method capable of quickly and effectively designing a crack-resistant mask layout in a full-chip scale, a mask manufacturing method including the mask layout design method, and a mask layout are provided. The mask layout design method includes designing a full-chip layout with respect to a mask; extracting a representative pattern from the full-chip layout; detecting a stress weak point in the representative pattern; verifying the stress weak point by forming a pattern on a wafer; and changing a design rule with respect to the full-chip layout.