Mask Generation Model Training for Low-Complexity Lithography Masks
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Solution Overview
Problem
Existing mask generation methods in photolithography result in high complexity masks, which are difficult to use in large-scale integrated circuit layout optimization, leading to deviations in pattern formation and affecting chip performance, throughput, and yield.
Innovation Solution
A method for training a mask generation model by inputting pre-defined chip layouts into a mask generation model, determining predicted masks using a photolithography physical model, and adjusting model parameters based on mask complexity to reduce complexity, using a combination of perimeter sums and loss functions to achieve low-complexity masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If deep learning algorithm or pixelation-based inverse lithography technology is used to generate mask, then pattern formation quality is improved, but mask complexity increases
Solution Approach 1:
The patent introduces mask complexity as a new parameter in the loss function, transforming the mask generation problem from purely pattern-matching to a multi-objective optimization problem. By adding the complexity parameter (calculated as perimeter of mask graphics) to the loss function, the system dynamically adjusts the optimization criteria to balance pattern quality and mask simplicity, resolving the contradiction between high-quality pattern formation and low mask complexity.
Solution Approach 2:
The patent implements a feedback mechanism where the generated mask is evaluated not only for pattern accuracy but also for complexity metrics. The complexity feedback is incorporated into the loss function, creating a closed-loop optimization process that continuously adjusts mask design to maintain both quality and simplicity, preventing the escalation of mask complexity that occurs in traditional methods.
2Ease of manufacture
If mask complexity is reduced for ease of manufacture, then manufacturing cost and time are improved, but pattern formation accuracy deteriorates
Solution Approach 1:
The patent changes the optimization parameters by incorporating complexity weighting in the loss function. This allows the system to find optimal masks that satisfy both manufacturing simplicity and pattern accuracy requirements simultaneously, rather than treating them as opposing goals. The weighted combination enables flexible adjustment based on specific manufacturing constraints.
Solution Approach 2:
The patent changes the optimization parameters by incorporating complexity weighting in the loss function. This allows the system to find optimal masks that satisfy both manufacturing simplicity and pattern accuracy requirements simultaneously, rather than treating them as opposing goals. The weighted combination enables flexible adjustment based on specific manufacturing constraints.
3Loss of time
If traditional mask generation methods are used, then calculation time is reduced, but mask complexity and transferability are worsened
Solution Approach 1:
The patent replaces traditional iterative mechanical optimization methods with a deep learning-based automated optimization system. The neural network automatically learns the complex mapping between layout and optimal mask design, incorporating complexity constraints directly into the learning objective. This substitution dramatically reduces calculation time while producing masks with controlled complexity, as the model learns efficient representations during training.
Data Source
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AI summary
The present disclosure provides a method for training a mask generation model, a method and an apparatus for mask generation, and a storage medium, including: obtaining a set of training samples, a training sample comprising a pre-defined layout of a chip sample and a mask of a pre-defined layout, for at least one training sample, using the pre-defined layout of the chip sample as an input for a mask generation model to obtain a predicted mask of the pre-defined layout as an output; inputting the predicted mask of the pre-defined layout into a photolithography physical model to obtain a wafer pattern corresponding to the predicted mask; determining complexity of the predicted mask of the pre-defined layout based on a sum of perimeters of a plurality of patterns included in the pre-defined layout of the chip sample and a perimeter of the predicted mask of the pre-defined layout; and adjusting a parameter of the mask generation model based on the pre-defined layout of the chip sample, the wafer pattern corresponding to the predicted mask of the pre-defined layout, the mask of the pre-defined layout, the predicted mask of the pre-defined layout, and the complexity of the predicted mask of the pre-defined layout until a training stop condition is met, to obtain a trained mask generation model.