Mask Optimization for Multi-Layer Contacts in Semiconductor Devices
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Solution Overview
Problem
The existing semiconductor fabrication process requires multiple masks to form multilayer contacts, leading to congestion and inefficiencies, particularly in forming contacts to gate devices and doped regions, where features often violate minimum pitch and spacing rules, affecting the resolution and accuracy of the exposure process.
Innovation Solution
The process optimizes mask placement by moving features from the gate contact mask to the second layer mask and splitting features as necessary to maintain electrical connections, using a computing system with modeling software to analyze and adjust mask patterns, ensuring features adhere to spacing rules and minimizing congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple masks are used to form multilayer contacts, then contacts to gate devices and doped regions can be formed separately, but feature congestion occurs and minimum pitch and spacing rules are violated
Solution Approach 1:
The patent combines the formation of contacts to gate devices and contacts to doped regions into a single mask pattern where possible. By merging these contact formations, the patent reduces the total number of masks required while maintaining the ability to form both contact types with appropriate spacing, thereby reducing mask complexity without sacrificing manufacturing precision
2Area of stationary object
If features are placed closely on masks to reduce congestion, then mask area is reduced, but minimum pitch and spacing rules are violated
Solution Approach 1:
The patent applies different spacing requirements to different regions of the mask pattern. By identifying areas where contacts to gate devices and contacts to doped regions can be locally optimized with appropriate spacing, the patent maintains manufacturing precision while reducing overall mask area through selective local adjustments rather than uniform spacing throughout
3Reliability
If separate masks are used for different contact layers, then electrical connections can be formed independently, but fabrication process time increases
Solution Approach 1:
The patent merges the patterning steps for contacts to gate devices and contacts to doped regions into a single exposure step using a combined mask pattern. This consolidation reduces the number of separate fabrication steps required while maintaining the ability to form reliable electrical connections for both contact types, thereby reducing fabrication process time without compromising connection reliability
Data Source
AI summary
A semiconductor device includes two elongated active regions that include source/drain regions for multiple transistor devices, a first contact layer that includes an electrical connection between the two active regions, a second contact layer that includes a connection between two gate lines, and a gate contact layer that provides connections to the gate lines.