Multi-Layer Mask Optimization for IC Overlap Regions
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Solution Overview
Problem
Current mask layout optimization techniques are limited by local search heuristics, which often result in suboptimal solutions and fail to account for the interactions between different layers of an integrated circuit (IC) during the manufacturing process.
Innovation Solution
A multi-layer aware mask optimization method that iteratively generates simulated wafer images for each layer, modifies the mask images to improve pattern fidelity and process window, and considers the interactions and overlaps between components across multiple layers to optimize the mask layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If local search heuristics are used for mask layout optimization, then computational time is reduced, but solution quality deteriorates
Solution Approach 1:
The patent segments the mask layout optimization into two distinct phases: a global optimization phase that explores the entire solution space using multi-layer awareness, and a local refinement phase that applies heuristic optimizations. This segmentation allows the system to achieve both high solution quality through global exploration and efficient computational time through localized refinement, resolving the contradiction between optimization thoroughness and computational cost.
Solution Approach 2:
The patent performs preliminary global optimization using multi-layer aware methods before applying local heuristic refinements. By conducting the comprehensive global search first to identify promising regions, the system establishes a solid foundation that subsequent local optimizations can efficiently refine, thereby reducing the time needed for final optimization while maintaining high solution quality.
2Device complexity
If single-layer mask optimization is performed, then computational complexity is reduced, but manufacturing reliability deteriorates
Solution Approach 1:
The patent transitions from single-layer optimization to multi-layer optimization by adding the dimension of layer interactions. The system simultaneously considers mask layouts across multiple layers and their interactions during the optimization process, enabling the identification of solutions that ensure proper alignment and overlap between layers. This dimensional expansion increases manufacturing reliability by accounting for inter-layer dependencies while managing computational complexity through structured optimization approaches.
Solution Approach 2:
The patent merges multiple single-layer optimization problems into a unified multi-layer optimization framework. By combining the optimization of mask layouts for different layers and incorporating their interactions into a single optimization process, the system achieves more reliable manufacturing outcomes. The merged approach allows the system to consider global constraints and inter-layer relationships that would be missed in isolated single-layer optimizations.
3Ease of operation
If traditional heuristic methods are used, then ease of operation is maintained, but manufacturing precision deteriorates
Solution Approach 1:
The patent implements feedback mechanisms that continuously monitor and evaluate the quality of mask layout optimizations against manufacturing constraints and desired outcomes. The system uses this feedback to guide the optimization process, adjusting parameters and directions to achieve higher pattern fidelity while maintaining operational ease. The feedback loop ensures that the optimization remains aligned with manufacturing requirements without requiring overly complex manual intervention.
Data Source
AI summary
Some embodiments provide a method for optimizing a mask layout generated from a design layout of an IC. Based on an initial mask layout for a first layer, the method generates a simulated wafer image including shapes representing IC components of the layer, including a first component that has a relationship with a second component on a second layer of the design layout. The method identifies, in the simulated wafer image, (i) a first set of regions of a first shape of the first component that overlap with a second shape of the second component and (ii) a second set of regions of the first shape that do not overlap with the second shape. To improve overlap between the first shape's first set of regions and the second shape, the method modifies the initial mask layout to produce a modified mask layout.