Mask Pattern Analysis Segmentation for Semiconductor Lithography
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Solution Overview
Problem
The optical rule check (ORC) process in semiconductor lithography is time-consuming, especially as feature sizes decrease and device density increases, requiring a more systematic review method to efficiently inspect aerial images and identify potential defects in mask patterns.
Innovation Solution
A pattern analysis system that groups polygons in a circuit layout into polygon groups, identifies potential defect areas, determines representing points, and compares distribution patterns using geometrical operations like rotation and mirroring to efficiently identify and categorize defect-prone areas, thereby reducing the time required for ORC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If aerial images are reviewed one by one in the ORC process, then each image can be inspected in detail, but the time consumption becomes excessive
Solution Approach 1:
The patent segments the aerial image into multiple sub-images based on polygon groups. Each sub-image contains a manageable number of polygons, allowing parallel processing while maintaining inspection thoroughness. This segmentation enables the system to process complex layouts efficiently without sacrificing detail inspection capability
Solution Approach 2:
The patent applies partial action by focusing inspection resources on critical areas identified through defect pattern analysis. Instead of uniformly processing all areas with the same level of detail, the system identifies and prioritizes regions with higher defect probability, reducing overall processing time while maintaining high detection accuracy for critical areas
2Quantity of substance
If the number of polygons in circuit layout increases due to higher device density, then more patterns can be processed, but the complexity of pattern analysis increases
Solution Approach 1:
The patent divides the large circuit layout into multiple polygon groups, each containing a subset of polygons. This segmentation reduces the complexity of analyzing the entire layout at once by breaking it into smaller, more manageable units that can be processed independently and in parallel
Solution Approach 2:
The patent introduces a hierarchical dimension to the analysis process by organizing polygons into groups and then analyzing defect patterns across these groups. This dimensional organization transforms the complex single-level analysis problem into a structured multi-level process, making high-density layouts more tractable
3Ease of manufacture
If traditional ORC methods are used without systematic review, then the process is simpler to implement, but the efficiency of mask production decreases
Solution Approach 1:
The patent performs preliminary actions by pre-processing the aerial image into organized polygon groups and pre-identifying potential defect areas before detailed analysis. This preliminary organization simplifies subsequent analysis steps and enables more efficient processing, improving overall mask production efficiency without significantly increasing implementation complexity
Data Source
AI summary
A pattern analysis method includes the steps of: grouping a plurality of polygons in a circuit layout into a plurality of polygon groups; locating a potential defect area of each polygon group according to an aerial image of the circuit layout; determining a representing point of the potential defect area of each polygon group; determining representing points of the plurality of polygons in each polygon group; and comparing a distribution pattern of the representing points of the plurality of polygons relative to the representing point of the potential defect area in one of the polygon groups with a distribution pattern of the representing points of the plurality of polygons relative to the representing point of the potential defect area in another of the polygon groups. The steps aforesaid are executed by a processor in a computer system.