Mask Pattern Design for Semiconductor Yield Optimization
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Solution Overview
Problem
Large semiconductor layouts exceeding 0.1 cm2 require extensive processing time for lithography simulation, making it impractical to quantify defects and evaluate optimal yield due to the complexity of trade-off relations in layout robustness methods, and existing methods struggle to provide systematic yield information as feedback to manufacturing processes.
Innovation Solution
A method involving dividing design layout data into regions, performing transfer simulations, and analyzing process windows with multiple conditions to extract and compute yield from regions prone to defects, allowing for focused process window analysis and reduced calculation time by identifying patterns outside dimension allowance values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If lithography simulation is performed on large semiconductor layouts exceeding 0.1 cm2, then comprehensive defect quantification and yield evaluation can be achieved, but processing time becomes excessively long and calculation becomes impractical
Solution Approach 1:
The patent divides the large semiconductor layout into multiple smaller regions, performing lithography simulation on each region separately. This segmentation allows comprehensive defect analysis without requiring excessive processing time, as each smaller region can be simulated independently and more efficiently than the entire large layout at once.
Solution Approach 2:
The patent extracts and identifies specific regions that are prone to defects based on initial simulation results. By focusing subsequent detailed process window analysis only on these extracted high-risk regions rather than the entire layout, the method achieves accurate defect quantification while significantly reducing overall calculation time.
2Reliability
If process window analysis is performed with multiple conditions on extracted regions, then systematic yield can be accurately computed, but calculation complexity increases
Solution Approach 1:
The patent applies different analysis depths to different regions: detailed process window analysis with multiple conditions is performed only on extracted regions prone to defects, while other regions receive less intensive analysis. This local quality approach maintains high systematic yield accuracy for critical areas without unnecessarily increasing overall calculation complexity.
Solution Approach 2:
The patent performs preliminary lithography simulation to identify and extract regions prone to defects before conducting the more complex process window analysis. This preliminary action filters out regions that don't require intensive analysis, thereby reducing the complexity of subsequent systematic yield computation while maintaining accuracy where it matters most.
Data Source
AI summary
A mask pattern design method includes: dividing design layout data for a pattern into multiple regions and extracting any region wherein transfer dimensions obtained from a transfer simulation of the pattern from the plurality of regions exceeds a predetermined allowance range; setting a process window of which multiple transfer conditions of the pattern data from the region extracted by the process are each changed, and computing transfer dimensions obtained from a transfer simulation with each transfer condition with the process window; and extracting the transfer conditions wherein the transfer dimension obtained from the transfer simulation with each transfer condition with the process window exceeds a predetermined allowance range, and computing yield from an occurrence probability regarding the transfer condition.