Mask Pattern Edge Widening for Uniform Wafer Etching
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Solution Overview
Problem
Existing integrated circuit fabrication methods result in non-uniform mask patterns due to non-uniform etching characteristics, leading to complications in wafer-level processing and poor device yield and reliability.
Innovation Solution
Selectively widening mask patterns near the edge of semiconductor wafers by depositing a second electrically insulating layer with temperature-dependent deposition rate characteristics, which compensates for narrower edge portions, and controlling the wafer temperature to achieve uniform critical dimensions across the wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography techniques are used to pattern mask layers, then mask patterns can be formed across the wafer, but the mask patterns exhibit non-uniform lateral dimensions with edge portions being narrower than center portions
Solution Approach 1:
The patent applies local quality by creating a non-uniform temperature distribution across the wafer surface during deposition, with the wafer center maintained at a higher temperature than the edge regions. This temperature gradient causes the deposited material to have different deposition rates at different locations, specifically thicker deposition at the center and thinner at the edges, thereby compensating for the inherent non-uniformity in mask pattern dimensions and achieving uniform critical dimensions across the entire wafer.
Solution Approach 2:
The patent changes the temperature parameter during the deposition process to resolve the contradiction. By controlling the wafer temperature profile (maintaining higher temperature at the center and lower at the edges), the deposition rate is modified locally to compensate for etching non-uniformity, transforming the temperature parameter into a control variable that achieves uniform mask pattern dimensions across the wafer.
2Ease of manufacture
If uniform etching is applied across the wafer, then processing is simplified, but edge portions of mask patterns become narrower than center portions due to wafer-scale etching characteristics
Solution Approach 1:
The patent applies preliminary anti-action by intentionally creating a non-uniform deposited layer with thicker material at the wafer center and thinner material at the edges before the etching process. This pre-compensation layer counteracts the expected non-uniform etching effects, ensuring that after etching, the critical dimensions are uniform across the entire wafer surface, thereby preventing the anticipated dimensional variation.
Solution Approach 2:
The patent modifies the deposition process parameters by implementing a controlled temperature gradient across the wafer surface. This parameter change in the deposition stage creates a compensatory thickness variation in the deposited layer that opposes and cancels out the non-uniformity introduced during subsequent etching, achieving uniform critical dimensions despite uniform etching conditions.
3Productivity
If mask patterns with varying dimensions are produced, then photolithographic patterning may proceed, but device yield and reliability deteriorate due to non-uniform critical dimensions
Solution Approach 1:
The patent applies preliminary action by performing a compensatory deposition step with controlled non-uniform temperature distribution before the photolithographic patterning process. This preliminary deposition creates a thickness profile that pre-compensates for expected dimensional variations, ensuring that subsequent patterning produces uniform critical dimensions across the wafer, thereby maintaining high device yield and reliability without sacrificing productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures more uniform center-to-edge critical dimensions, improving device yield and reliability by compensating for etching variations and maintaining consistent patterning across the wafer.
Implementation Method 1
depositing a second electrically insulating layer having temperature-dependent deposition rate characteristics on the mask pattern. These temperature-dependent characteristics result in a second electrically insulating layer that is thicker on the peripheral portions of the semiconductor wafer and thinner on the interior portions of the semiconductor wafer
Implementation Method 2
the step of depositing the second electrically insulating layer is performed while simultaneously controlling a temperature of the semiconductor wafer to have a nonuniform center-to-edge temperature profile
Data Source
AI summary
Methods of forming integrated circuit devices include steps to selectively widen portions of a mask pattern extending adjacent an outer edge of a semiconductor wafer. These steps to selectively widen portions of the mask pattern are performed so that more uniform center-to-edge critical dimensions (CD) can be achieved when the mask pattern is used to support photolithographically patterning of underlying layers (e.g., insulating layers, antireflective coatings, etc.).