Mask Pattern Process Margin Verification Using Intermediate Stage Models
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Solution Overview
Problem
Existing techniques for verifying process margins in photolithography, such as using etch models or rule-based tables, often yield unsatisfactory results due to distortions caused by optical diffraction and other manufacturing processes, leading to inaccuracies in defining patterns on semiconductor wafers.
Innovation Solution
The method involves modifying a mask pattern using a first model, such as an etch model, and then verifying the process margin using a second model, like a resist model, to estimate and correct distortions at intermediate stages, allowing for more accurate verification of the mask pattern's process margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an etch model is used to modify a mask pattern, then the mask pattern can be adjusted to compensate for etching deviations, but the verification of process margin becomes inaccurate due to optical diffraction effects not being accounted for
Solution Approach 1:
The verification process is segmented into multiple independent tests: a first test using an etch model to evaluate etching process margin, and a second test using a resist model to evaluate resist processing margin. Each test independently verifies different aspects of the manufacturing process, allowing comprehensive process margin assessment without the inaccuracies of relying on a single model.
Solution Approach 2:
A resist model is introduced as an intermediary verification tool to assess the process margin of mask patterns after etch model modification. The resist model acts as a mediator that evaluates whether the modified mask pattern will produce the desired wafer pattern when subjected to resist processing, thereby compensating for the limitations of using only an etch model.
2Ease of manufacture
If a rule-based table is used to correct a mask pattern, then design rules can be enforced, but the method yields unsatisfactory results in complex situations involving optical diffraction and intermediate stage distortions
Solution Approach 1:
The verification process uses parameter changes by selecting different process models (etch model vs. resist model) and their associated tests based on the specific manufacturing stage being evaluated. The system dynamically adjusts which model and test parameters are applied depending on whether the focus is on etching process margin or resist processing margin, enabling accurate verification across different manufacturing conditions.
Data Source
AI summary
Verifying a process margin for a mask pattern includes receiving the mask pattern for patterning features on a semiconductor wafer. The mask pattern is modified according to a wafer pattern model operable to estimate a wafer pattern resulting from the mask pattern. An intermediate stage model is selected to apply to a portion of the mask pattern, where the intermediate stage model is operable to estimate an intermediate stage of the wafer pattern. A process margin of the portion is verified by selecting a test of the intermediate stage model, and performing the test on the portion to verify the process margin of the portion.