Mask Pattern Selective Epitaxy for Memory Devices

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Solution Overview

Problem

The challenge in semiconductor memory device fabrication lies in achieving high integration with fine patterns while maintaining performance, particularly in the peripheral circuit region, where existing exposure techniques are costly and difficult to implement effectively.

Innovation Solution

A method involving a substrate with distinct regions, where a mask pattern is used to form word lines and channel epitaxial layers, allowing for the selective growth of silicon germanium layers in PMOS regions while simplifying the process and reducing substrate damage, thereby enhancing transistor performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If new exposure techniques are used for forming fine patterns, then manufacturing precision is improved, but device complexity and fabrication cost increase

Engineering Contradiction:
Improvefine pattern formationVSAvoidexposure technique complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The method performs preliminary patterning actions by forming a mask pattern that defines both word line regions and PMOS regions before subsequent processing steps. This preliminary mask pattern serves as a template for multiple subsequent operations including selective etching and epitaxial growth, eliminating the need for multiple exposure steps and reducing overall process complexity while maintaining fine pattern precision

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If multiple separate mask patterns are used for word lines and PMOS regions, then manufacturing precision is improved, but ease of manufacture deteriorates

Engineering Contradiction:
Improvepattern alignmentVSAvoidfabrication process simplicity
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The invention merges the mask patterns for word lines and PMOS regions into a single integrated mask pattern. This unified mask simultaneously defines both the word line trenches in the cell array region and the PMOS region boundaries, allowing both structures to be formed in a coordinated manner through selective etching and epitaxial growth, thereby simplifying the fabrication process while maintaining precise alignment between different structures

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The single mask pattern serves multiple functions: it defines word line trench positions in the cell array region, defines PMOS region boundaries, and acts as a barrier during selective epitaxial growth. This multi-functional mask eliminates the need for separate masking steps for different structures, improving ease of manufacture while preserving manufacturing precision through its universal applicability across multiple process steps

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Ease of manufacture

If conventional etching methods are used without selective barriers, then ease of manufacture is improved, but manufacturing precision deteriorates due to substrate damage

Engineering Contradiction:
Improveetching process simplicityVSAvoidsubstrate integrity
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The mask pattern serves as an intermediary barrier material during the etching and epitaxial growth processes. It protects specific regions from etching and prevents unwanted epitaxial growth, acting as a mediator that enables selective processing without requiring complex substrate preparation or additional protective layers. This intermediary function maintains substrate integrity while keeping the process relatively simple

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the fabrication of highly integrated semiconductor memory devices with improved performance by simplifying the manufacturing process, reducing substrate damage, and enhancing carrier mobility through the use of silicon germanium layers in PMOS transistors.

Implementation Method 1

forming a channel epitaxial layer on the second region of the substrate while using the mask pattern as a barrier to growth of the channel epitaxial layer on the first region of the substrate

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS20180122811A1Methods of fabricating memory devices
Publication Date: 2018.05.03 SAMSUNG ELECTRONICS CO LTD
  • US20180122811A1 patent drawing
  • US20180122811A1 patent drawing
  • US20180122811A1 patent drawing

AI summary

Methods of fabricating a memory device are provided. The methods may include forming a mask pattern including line-shaped portions that are parallel to each other and extend on a first region of a substrate. The mask pattern may extend on a second region of the substrate. The methods may also include forming word line regions in the first region using the mask pattern as a mask, forming word lines in the word line regions, respectively, and removing the mask pattern from the second region to expose the second region. The mask pattern may remain on the first region after removing the mask pattern from the second region. The methods may further include forming a channel epitaxial layer on the second region while using the mask pattern as a barrier to growth of the channel epitaxial layer on the first region.