Mask Pattern Verification Apparatus for Semiconductor Fabrication

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Solution Overview

Problem

The increasing complexity and miniaturization of semiconductor devices lead to longer verification times (TAT) in mask pattern verification, as existing methods require extensive verification of all circuit patterns due to limited libraries of OPC non-adaptation patterns, resulting in inefficiencies and prolonged production times.

Innovation Solution

A mask pattern verification apparatus and method that includes a library registration portion, memory for design and verification patterns, and CPU components for pattern matching, OPC, and verification, allowing for efficient extraction and verification of clean circuit patterns, reducing the need for full-pattern verification and thus shortening TAT.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If OPC non-adaptation patterns are saved in a library for verification, then verification TAT is intended to be shortened, but the library capacity is finite and cannot cover all possible circuit patterns

Engineering Contradiction:

Improveverification TATVSAvoidlibrary coverage

Core Design Contradiction:

Loss of timeVSAdaptability or versatility

Solution Approach 1:

The verification process is segmented into two stages: first, pattern matching against the library is performed to identify potential matches; second, only non-matched patterns undergo full verification. This segmentation allows the system to leverage the library for quick filtering while maintaining comprehensive verification coverage for unique patterns.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The library of OPC non-adaptation patterns is prepared in advance and used for preliminary pattern matching before full verification. This preliminary action filters out common patterns that can be quickly identified, allowing the system to skip full verification for these cases and thereby reduce overall verification TAT.

Inventive Principle:

Principle #10Preliminary action

2Manufacturing precision

If all circuit patterns are verified to ensure device yield, then manufacturing precision is improved, but verification TAT is increased

Engineering Contradiction:

Improvedevice yieldVSAvoidverification TAT

Core Design Contradiction:

Manufacturing precisionVSLoss of time

Solution Approach 1:

Instead of performing full verification on all circuit patterns, the system applies partial verification only to non-matched patterns. The pattern matching stage provides a preliminary filter that handles common cases, while full verification is applied selectively to the remaining patterns, achieving sufficient verification coverage without the time cost of verifying everything.

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The pattern matching process serves as an intermediary between the library and full verification. It acts as a filtering mechanism that identifies patterns requiring full verification, thereby reducing the workload on the verification system while maintaining quality assurance for critical cases.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Adaptability or versatility

If circuit patterns are enlarged and made more complex to increase device functionality, then adaptability is improved, but verification TAT is increased

Engineering Contradiction:

Improvecircuit functionalityVSAvoidverification TAT

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The verification approach segments complex circuit patterns into matchable components against the library. By breaking down the verification task into pattern matching followed by selective full verification, the system can handle complex patterns more efficiently without being overwhelmed by their complexity.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS8110413B2Mask pattern verification apparatus, mask pattern verification method and method of fabricating a semiconductor device

Publication Date: 2012.02.07 KIOXIA CORP

AI summary

In one embodiment, a mask pattern verification apparatus is disclosed. The mask pattern verification apparatus can include a library registration portion registered a clean circuit pattern, a memory portion saved a design circuit pattern, a verification circuit pattern, a verification mask pattern, and a verification wafer pattern, a mask verification portion performing mask verification to the verification mask pattern, a lithography verification portion performing lithography verification to the verification wafer pattern, and a CPU including a library registration circuit registering the clean circuit pattern to the library registration portion, a pattern matching circuit verifying the clean circuit pattern being set or not in the design circuit pattern, a verification pattern extraction circuit extracting the verification circuit pattern from the design circuit pattern, an OPC circuit performing OPC to the verification circuit pattern, a mask verification circuit controlling the mask verification portion, and a lithography verification circuit controlling the lithography verification portion.