Mask Permutation Instruction for Sparse Loop Vectorization

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Solution Overview

Problem

Current processor technologies face challenges in achieving performance gains through vectorization, particularly in sparse and branchy loops, due to complex dynamic control flow and the requirement for costly instructions like gather and scatter, which limits the exploitation of parallelism in vector or SIMD computing.

Innovation Solution

An instruction is introduced to permute a mask, allowing for reads and writes to correct locations, enabling the vectorization of certain types of code by modifying a mask operand, regardless of its size or intended use, through a specific instruction format that includes opcode, source, and destination operand identifiers, facilitating improved execution and data manipulation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If vectorization is attempted on sparse and branchy loops, then parallelism exploitation is improved, but execution complexity increases due to costly gather and scatter instructions

Engineering Contradiction:
Improveparallelism exploitationVSAvoidexecution complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent extracts the mask permutation operation from the complex gather/scatter sequence and implements it as a dedicated PERMUTE MASK instruction. This separates the masking function from the data movement operations, allowing the mask to be independently permuted without requiring costly gather/scatter instructions, thereby reducing execution complexity while maintaining parallelism exploitation

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a mask register as an intermediary component that holds the permuted mask values. This mask register acts as a mediator between the permutation operation and the final data access operations, enabling efficient mask manipulation without directly involving complex memory access patterns, thus simplifying the overall execution

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If complex dynamic control flow is present in vectorized code, then code flexibility is improved, but vectorization effectiveness deteriorates

Engineering Contradiction:
Improvecode flexibilityVSAvoidvectorization effectiveness
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by performing mask permutation before the actual data access operations. By pre-permuting the mask according to the control flow requirements, the code can handle complex dynamic control flow patterns without interfering with the vectorization effectiveness, as the mask is already prepared in the correct permutation state when needed

Inventive Principle:
Principle #10Preliminary action

3Productivity

If gather and scatter instructions are used for vectorization, then data movement capability is improved, but instruction cost increases

Engineering Contradiction:
Improvedata movement capabilityVSAvoidinstruction cost
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent replaces the expensive gather and scatter instructions with a cheaper PERMUTE MASK instruction that operates on masks in a dedicated mask register. This new instruction is designed to be more efficient and less costly, achieving the same data movement capability through a simpler, more economical operation that does not require the complex memory access patterns of gather/scatter

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Data Source

PatentUS9921841B2System and method for executing an instruction to permute a mask
Publication Date: 2018.03.20 INTEL CORP
  • US9921841B2 patent drawing
  • US9921841B2 patent drawing
  • US9921841B2 patent drawing

AI summary

A processor is described, including a fetch circuit to fetch an instruction, including a first source operand identifier, a second source operand identifier, and a destination operand identifier, a decode circuit to decode the instruction, a data retrieval circuit to retrieve data associated with the first source operand identifier and the second source operand identifier, and an execution circuit. In some embodiments, the execution circuit is configured to determine whether a first element of the data associated with the first source operand identifier is set, if the first element is set, to retrieve a destination index from a corresponding second element of the data associated with the second source operand identifier, and to use the destination index to select and set a destination element of data associated with the destination operand identifier.