Patterned Mask Pitch Reduction for Integrated Circuit Features
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Solution Overview
Problem
Current integrated circuit fabrication methods are limited by the resolution of photolithographic equipment, making it difficult to reduce the pitch below the minimum producible size, leading to inaccuracies in feature reproduction and varying results.
Innovation Solution
A method involving the formation of a patterned mask layer with a first pitch, trimming it to expose un-doped regions, introducing dopants to create doped regions with a smaller second pitch, and selectively removing un-doped regions to form features with a reduced pitch, allowing for sub-lithographic feature sizes without overlay issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithographic equipment is used to define features in photoresist, then features can be formed with lithographic resolution, but the minimum feature size is limited by the machine's resolution capability, preventing pitch reduction below the minimum lithographic pitch
Solution Approach 1:
The pitch reduction process is segmented into multiple distinct steps: (1) forming initial features at lithographic pitch using photolithography, (2) trimming features to create spacing, (3) introducing dopants to create doped and un-doped regions, and (4) selectively removing un-doped regions. This segmentation allows each step to be optimized independently, achieving sub-lithographic pitch while maintaining manufacturing precision through controlled material removal rather than direct patterning.
Solution Approach 2:
The method performs preliminary actions by first forming features at the lithographic minimum pitch, then trimming these features to create gaps. Dopants are introduced in advance to specific regions before the final selective removal step. These preliminary actions prepare the structure for the subsequent pitch reduction, enabling the final features to be smaller than the original lithographic features while maintaining control over the final dimensions.
2Productivity
If pitch is reduced below minimum lithographic pitch, then circuit density increases, but the photoresist regions exposed to radiation fail to correspond to the mask plate pattern, resulting in inaccurate feature reproduction
Solution Approach 1:
The patent uses dopants as an intermediary mechanism to transfer the pattern from the trimmed features to the final structure. The dopants are introduced through the trimmed features into the underlying layer, creating doped regions that serve as a intermediate pattern. This intermediary doping step allows the final selective removal to accurately reproduce the intended sub-lithographic pattern without requiring the photoresist to directly define features smaller than the lithographic minimum, thus maintaining feature reproduction accuracy while achieving higher circuit density.
3Length of moving object
If prior methods are used to reduce pitch below minimum pitch, then pitch reduction is attempted, but the methods are difficult to control and show varying results
Solution Approach 1:
The method changes multiple parameters to achieve reliable pitch reduction: (1) changes the physical state and concentration of dopants introduced into the structure, (2) changes the dimensions of trimmed features to create appropriate spacing, and (3) changes the selectivity of the final removal process by utilizing the differential properties of doped versus un-doped regions. These parameter changes are systematically controlled at each step, providing multiple degrees of freedom for optimization and ensuring reliable, repeatable results rather than varying outcomes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of integrated circuits with reduced pitch, improving density and functionality by accurately transferring patterns with controlled dimensions and increased flexibility in production, while maintaining device performance and yield.
Implementation Method 1
introducing dopants into the second material layer not covered by the trimmed patterned mask layer
Implementation Method 2
introducing dopants into the second material layer not covered by the trimmed patterned mask layer
Data Source
AI summary
A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.