Address Translation Circuit Using Mask Registers for Memory Testing
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Solution Overview
Problem
Conventional test apparatuses face increased maintenance and management costs due to the high capacitance requirements for translating memory input addresses into physical addresses as memory device performance increases, making it difficult to efficiently access storage cells for detecting badness in memory devices.
Innovation Solution
A test apparatus with an address generating circuit, mask registers, mask arithmetic circuits, logical operation circuits, and a translation memory that uses logical operations to generate memory input addresses from physical addresses, allowing for flexible address translation and reducing the need for large translation memory capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a translation memory is used to translate physical addresses into memory input addresses, then address translation can be achieved, but the translation memory capacitance increases with memory device performance, leading to increased maintenance and management costs
Solution Approach 1:
The patent segments the address translation process into multiple independent logic circuits, each handling specific address bits. Instead of using a single large translation memory, the system divides the translation function across multiple smaller logical units that operate in parallel, reducing the overall memory capacitance requirement while maintaining full address translation capability.
Solution Approach 2:
The patent replaces the traditional translation memory mechanism with a logic circuit-based system. By using logical operations (AND, OR, XOR gates) and mask registers instead of memory storage, the system eliminates the need for large capacitance translation memory while achieving the same address translation function through computational logic.
2Productivity
If the bus width of address increases with high performance memory device, then memory performance improves, but necessary capacitance of translation memory increases, making it difficult to maintain and manage
Solution Approach 1:
The patent introduces dynamic mask registers that can be programmably configured to adapt to different address translation requirements. This dynamic configuration allows the logic circuits to handle varying bus widths and translation patterns without requiring proportional increases in translation memory capacitance, enabling the system to scale with memory performance while maintaining manageable complexity.
Solution Approach 2:
The patent changes the fundamental parameter of address translation from memory storage capacity to logical operation complexity. By using configurable mask registers and logic gates, the system can adjust translation parameters (such as which address bits are masked or inverted) without increasing hardware capacitance, allowing high-performance memory devices to be tested without proportionally increasing translation memory requirements.
3Reliability
If conventional translation memory is used for address translation, then address mapping can be achieved, but maintenance and management costs increase with high-performance memory devices
Solution Approach 1:
The patent implements self-service through programmable mask registers that can be configured via software or control signals. The address translation logic is controlled by configurable parameters rather than fixed hardware, allowing automatic adaptation to different memory layouts and translation schemes without requiring manual hardware reconfiguration or increasing maintenance complexity.
Data Source
AI summary
There is provided a test apparatus that tests a device under test. The test apparatus includes an address generating circuit that generates a physical address to be supplied to a memory block inside the device under test, a plurality of mask registers being provided in correspondence with a plurality of memory input bits constituting at least a part of a memory input address to be supplied to the device under test, where the plurality of mask registers set values indicating whether a plurality of physical bits constituting the physical address is masked every the physical bit, a plurality of mask arithmetic circuits being provided in correspondence with each of the plurality of memory input bits, where the plurality of mask arithmetic circuits respectively mask the physical address in accordance with the value of the mask register corresponding to this memory input bit, a plurality of logical operation circuits being provided in correspondence with each of the plurality of memory input bits, where the plurality of logical operation circuits respectively output bit data obtained by performing a predetermined logical operation on a masking result by the mask arithmetic circuit as the memory input bit, and an address supplier that supplies the input address including the plurality of memory input bits output from the plurality of logical operation circuits to the device under test.