Mask Reuse Methodology for Soft Logic Integration
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Solution Overview
Problem
The existing System-On-a-Chip (SoC) methodologies partially address design cost and complexity by reusing pre-designed components, but fail to efficiently address the increasing costs and complexities related to mask data preparation and mask building, particularly for soft logic components like glue logic and custom logic required in chip manufacturing.
Innovation Solution
A mask reuse methodology (MRM) process utilizing a generic array type cell structure mask and a custom blocking mask to implement soft logic, where the custom blocking mask positionsally corresponds with hard IP component cores, allowing for the printing of soft logic onto the die while avoiding areas with pre-fabricated hard IP blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If pre-designed IP components are integrated into SoC designs, then design cost and complexity are reduced, but mask data preparation and mask building costs still increase dramatically
Solution Approach 1:
The mask set is segmented into reusable masks for hard IP components and a separate custom logic mask for soft logic components. This segmentation allows each mask to be optimized independently - the reusable masks can be standardized across multiple chips while the custom logic mask addresses specific chip requirements, thereby reducing overall mask building costs despite increasing chip complexity.
Solution Approach 2:
Reusable masks for hard IP components are prepared in advance and can be stored for multiple uses. This preliminary action eliminates the need to recreate these masks for each new chip design, significantly reducing mask data preparation costs while allowing the design complexity to increase through integration of multiple pre-verified IP components.
2Ease of manufacture
If reusable partitioned masks are used for hard IP components, then mask set cost is reduced, but soft logic components still require separate mask creation
Solution Approach 1:
The reusable masks for hard IP components and the custom logic mask for soft logic are merged into a single integrated mask set. This merging allows both hard and soft logic to be fabricated together in one process, eliminating the need for separate mask creation steps and reducing overall mask data preparation complexity while maintaining the cost benefits of mask reuse.
Solution Approach 2:
The mask reuse methodology creates a universal framework that handles both hard IP components (through reusable masks) and soft logic components (through custom logic masks) within a single process. This multi-functional approach allows the same mask fabrication infrastructure to serve multiple purposes, reducing both cost and complexity.
3Adaptability or versatility
If chip fabrication includes both hard IP blocks and soft logic, then chip functionality is enhanced, but manufacturing time increases
Solution Approach 1:
The mask fabrication process maintains continuity by using a unified mask set that covers both hard IP blocks and soft logic components. This eliminates gaps or interruptions in the fabrication process that would occur with separate mask sets, allowing continuous processing and reducing overall manufacturing time while preserving full chip functionality.
Solution Approach 2:
Reusable masks for hard IP components are prepared in advance and stored for rapid deployment. When a new chip design is needed, these pre-prepared masks can be quickly combined with custom logic masks without requiring time-consuming recreation of the hard IP portion, thereby reducing manufacturing time while maintaining enhanced chip functionality.
Data Source
AI summary
A mask reuse methodology process in which the soft logic is implemented with a generic array type cell structure mask and a custom blocking mask. A method is provided comprising printing a set of component cores onto a die at predetermined locations with a reusable mask set; providing a custom blocking mask that includes opaque regions that positionally correspond with the component cores on the die; superimposing the custom blocking mask with a generic array type cell mask to form superimposed masks; and using the superimposed masks to print generic array type cells onto the die with the exception of the predetermined locations where the set of component cores reside.