Mask ROM Device 2-Bit Storage Integration
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Solution Overview
Problem
Conventional mask ROM devices are inadequate for applications requiring high integration and large data storage due to their limited capability of storing only 1-bit logic values, which complicates integration with other memory systems like 3D NAND flash memory devices and poses manufacturing inefficiencies.
Innovation Solution
A mask ROM device capable of storing 2-bit logic values, featuring a plurality of single-transistor memory cells with MOS transistors, where each memory cell's source terminal can be electrically coupled to a ground line or reference lines to read different logic values, allowing for improved integration and manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional mask ROM devices store only 1-bit logic values per memory cell, then the device structure is simple, but the integration density and data storage capacity are limited
Solution Approach 1:
The patent changes the parameter of logic values stored per memory cell from 1-bit to 2-bit. Each memory cell now stores one of four logic values (0, 1, 2, 3) by selectively coupling the source terminal to different reference lines (first reference line, second reference line, or ground line), thereby doubling the storage capacity without changing the basic single-transistor cell structure
Solution Approach 2:
The memory cell structure is made multi-functional by enabling it to store 2-bit logic values through selective source terminal coupling. The same basic memory cell structure can represent four different logic states, making the device more versatile and increasing integration density without requiring fundamentally different cell designs
2Ease of manufacture
If mask ROM device programming is performed with conventional 1-bit memory cells, then the programming process is straightforward, but the integration with 3D NAND flash memory systems becomes complex and area-inefficient
Solution Approach 1:
The patent merges the mask ROM device programming process with the 3D NAND flash memory device manufacturing process. The electrical connects (contacts and vias) used for programming the mask ROM device are integrated with those required for the 3D NAND flash memory, eliminating the need for separate dedicated programming connects and improving area efficiency
Solution Approach 2:
The electrical connects in the memory system are made multi-functional, serving both the programming of mask ROM devices and the manufacturing requirements of 3D NAND flash memory devices. This universal use of the same electrical connects simplifies integration and reduces the overall area required
3Adaptability or versatility
If dedicated electrical connects are formed throughout the memory system for mask ROM device programming, then the programming can be performed, but the layout constraints increase and area efficiency decreases
Solution Approach 1:
The patent combines the electrical connects required for mask ROM device programming with those required for 3D NAND flash memory device manufacturing. By merging these functions into a single set of electrical connects, the layout constraints are reduced and area efficiency is improved
Data Source
AI summary
A mask read only memory device is provided. Single-transistor memory cells are arranged in rows and columns. Each word line is associated with a corresponding row. Each bit line is associated with a corresponding column. Each first reference line selectively provides a first potential in a first phase and a second potential in a second phase. Each second reference line selectively provides the second potential in the first read phase and the first potential in the second phase. Each memory cell has a gate coupled to a word line, a drain coupled to a bit line and a source terminal either floating, grounded or coupled to one among a first reference line and a second reference line. One of first to fourth logic values is read during a read operation of the memory cell.