Mask-saving RESURF Transistor Fabrication
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Solution Overview
Problem
The production of lateral high-voltage MOS transistors with double or multiple RESURF structures is complex and requires additional masking steps, increasing fabrication effort and cost.
Innovation Solution
A method that forms both the drain extension region and the doped region for a double RESURF structure in a single implantation step using the same mask, reducing the need for multiple mask openings and simplifying the fabrication process for complementary lateral high-voltage MOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a double or multiple RESURF structure is formed using separate masking steps for doped regions in the drift zone, then the breakthrough voltage is increased and on-resistance is reduced, but the fabrication complexity and manufacturing effort increase
Solution Approach 1:
The patent combines the formation of doped regions in the drift zone and drain extension regions into a single ion implantation step using a common masking step. This merging of previously separate process steps reduces fabrication complexity while maintaining the electrical performance benefits of the RESURF structure, directly addressing the contradiction between reliability improvement and fabrication complexity
2Reliability
If additional masking steps are used to form doped regions in the drift zone for RESURF structure, then the on-resistance is reduced through increased charge carrier concentration, but the productivity and manufacturing efficiency decrease
Solution Approach 1:
The invention merges the doping of drift zone regions and drain extension regions into one simultaneous ion implantation process step. This eliminates the need for additional masking steps that would otherwise be required to form the doped regions separately, thereby improving manufacturing efficiency and productivity while achieving the desired low on-resistance through the RESURF structure
Solution Approach 2:
The common mask used in the implantation step serves multiple functions: it defines both the doped regions in the drift zone and the drain extension regions simultaneously. This multi-functionality of the masking step reduces the total number of process steps required, directly improving manufacturing efficiency without compromising the electrical performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the efficient and cost-effective fabrication of integrated circuits with complementary lateral high-voltage MOS transistors of different conductivity types, reducing the complexity and effort required in the production process.
Implementation Method 1
forming at least one first doped region of the first conductivity type in the first active region and forming a drain extension region of the first conductivity type in the second active region which comprises a concurrent implantation of a dopant into the first and second active regions
Data Source
AI summary
Methods of forming, on a substrate, a first lateral high-voltage MOS transistor and a second lateral high-voltage MOS transistor complementary to said first one are disclosed. According to one embodiment, the method includes (1) providing a substrate of a first conductivity type including a first active region for said first lateral high-voltage MOS transistor and a second active region for said second lateral high-voltage MOS transistor and (2) forming at least one first doped region of the first conductivity type in the first active region and forming in the second active region a drain extension region of the second conductivity type extending from a substrate surface to an interior of the substrate, including a concurrent implantation of dopants through openings of one and the same mask into the first and second active regions. Forming of the at least one first doped region may be a sub step of a superior step of forming a double RESURF structure in the first lateral high-voltage MOS transistor, and forming the double RESURF structure may include forming doped RESURF regions as two first doped regions, one thereof above and one thereof below the drift region of the first lateral high-voltage MOS transistor, and as two further doped regions, one thereof above and one thereof below the drain extension regions of the second lateral high-voltage MOS transistor, wherein the first doped RESURF regions have an inverse conductivity type with respect to the drift region and the further doped regions have inverse conductivity type as compared to the drain extension region.