Mask Shift Resistance-Inductance Extraction for Multiple Patterning
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Solution Overview
Problem
The increasing optical proximity effect in integrated circuit manufacturing poses challenges as features become closer, exceeding the resolution limit of light sources, necessitating multiple patterning technologies to separate features into multiple masks, which complicates resistance, inductance, and capacitance calculations due to mask pattern shifts.
Innovation Solution
The method involves performing resistance inductance network extraction and timing analysis, accounting for mask pattern shifts during exposure, and using color bias techfiles to calculate capacitance, resistance, and inductance changes, allowing for the determination of optimal decompositions of semiconductor devices by simulating worst-case performance values across various mask shifts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple patterning masks are used to separate closely located features, then the resolution limit is overcome and feature density is enhanced, but mask pattern shifts occur during exposure causing inaccuracies in resistance, inductance, and capacitance calculations
Solution Approach 1:
The patent applies preliminary action by performing resistance inductance network extraction and timing analysis before final mask fabrication, accounting for potential mask pattern shifts during exposure. By simulating worst-case performance values across various mask shifts and using color bias techfiles to calculate capacitance, resistance, and inductance changes, the method prepares design data in advance that compensates for expected variations, ensuring accurate performance prediction despite subsequent mask shifts.
2Measurement precision
If mask pattern shifts are accounted for in resistance inductance network extraction, then performance calculation accuracy is improved, but computational complexity and processing time increase
Solution Approach 1:
The patent applies parameter changes by varying mask shift parameters within a defined range during simulation to establish worst-case performance values. By systematically changing shift parameters and corresponding performance metrics, the method efficiently identifies boundary conditions without requiring exhaustive simulation of every possible shift scenario, thus balancing accuracy with computational efficiency.
3Reliability
If worst-case performance simulation is performed across various mask shifts, then design robustness is improved, but device complexity and processing requirements increase
Solution Approach 1:
The patent applies the taking out principle by extracting and isolating the mask shift variable from the overall design simulation process. By focusing simulations specifically on worst-case mask shift scenarios rather than all possible variations, the method identifies critical performance boundaries without requiring full-system re-simulation for every parameter combination, thus reducing overall computational complexity while maintaining design robustness.
Data Source
AI summary
A system and method comprising providing a layout of an integrated circuit design, generating, by a processor, a plurality of multiple patterning decompositions from the layout, determining a maximum mask shift between the first mask and the second mask and simulating a worst-case performance value for each of the plurality of multiple patterning decompositions using one or more mask shifts within a range defined by the maximum mask shift. Further, each of the plurality of multiple patterning decompositions comprise patterns separated to a first mask and a second mask of a multiple patterning mask set.