Mask Simulation Model Calibration for OPC Error Reduction
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Solution Overview
Problem
Current methods for integrated circuit (IC) design and mask making are inadequate in reducing patterning errors and optimizing circuit performance and fabrication cost, particularly due to limitations in lithography printing capability and the interaction of mask diffraction with other factors during simulation.
Innovation Solution
A method involving the construction of a mask model and a compound lithography computational (CLC) model using historic data to simulate mask and wafer patterns, with calibration based on measured mask and wafer data to improve accuracy and reduce errors in optical proximity correction (OPC) processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If existing simulation methods are used for OPC and mask making, then the process is simpler, but patterning errors increase and manufacturing precision deteriorates
Solution Approach 1:
The patent segments the simulation process into two distinct calibration stages: mask model calibration using measured mask images, and CLC model calibration using measured wafer data. This segmentation allows each model to be calibrated independently with appropriate measurement data, improving overall simulation accuracy without creating an unmanageably complex integrated system.
Solution Approach 2:
The patent introduces mask images as an intermediary measurement medium between the mask making process and wafer patterning. By measuring actual mask images and using them to calibrate the mask model, the system obtains accurate intermediate data that bridges the gap between mask fabrication and final wafer results, enabling better error correction.
2Reliability
If mask diffraction is combined with other factors in simulation, then the simulation is more comprehensive, but the ability to isolate and correct mask-specific errors deteriorates
Solution Approach 1:
The patent separates mask diffraction effects from other lithography factors by implementing distinct calibration steps: first calibrating the mask model using only mask images (isolating mask diffraction), then calibrating the CLC model using wafer data (incorporating other factors). This segmentation enables precise isolation and correction of mask-specific errors while maintaining comprehensive simulation capability.
3Manufacturing precision
If OPC processes are optimized for better wafer results, then circuit performance improves, but fabrication cost increases
Solution Approach 1:
The patent implements a self-calibrating simulation system that uses actual measurement data from the fabrication process (mask images and wafer data) to automatically adjust and optimize the simulation models. This self-service approach eliminates the need for expensive trial-and-error physical experiments, reducing fabrication costs while improving wafer results through data-driven optimization.
Solution Approach 2:
The patent establishes feedback loops where measured mask images and wafer data are fed back into the simulation models for calibration. This feedback mechanism allows continuous optimization of OPC parameters based on actual process performance, improving circuit performance while reducing the need for costly re-spins and iterations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the accuracy of mask modeling and OPC processes, reducing errors and improving the effectiveness of mask pattern generation for IC fabrication by isolating mask diffraction effects and incorporating real-time data for better wafer contour simulation.
Implementation Method 1
The mask model is built to simulate a mask image on a semiconductor substrate during a lithography process to pattern the semiconductor substrate. The mask model considers two factors: mask diffraction and imaging projection.
Implementation Method 2
The mask pattern will cause diffraction of the light from the light source of the lithography system and the light is further projected through projection lens of the lithography system to form an image of the mask pattern on the wafer surface
Data Source
AI summary
An integrated circuit (IC) method is provided. The method includes building a mask model to simulate an aerial mask image of a mask, and a compound lithography computational (CLC) model to simulate a wafer pattern; calibrating the mask model using a measured aerial mask image of the mask; calibrating the CLC model using measured wafer data and the calibrated mask model; performing an optical proximity correction (OPC) process to a mask pattern using the calibrated CLC model, thereby generating a corrected mask pattern for mask fabrication. Alternatively, the method includes measuring a mask image of a mask optically projected on a wafer with an instrument; calibrating a mask model using the measured mask image; calibrating a CLC model using measured wafer data and the calibrated mask model; and performing an OPC process to a mask pattern using the calibrated CLC model, thereby generating a corrected mask pattern for mask fabrication.