Double Patterning Mask Trim for Semiconductor Yield

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Solution Overview

Problem

The conventional self-aligned double patterning (SADP) approach in semiconductor fabrication faces issues with uniformity of etching recessing and spacer bending, leading to manufacturing yield and performance challenges due to limitations in transferring layout patterns effectively.

Innovation Solution

A patterning method involving a first and second mask layer, where the second mask layer is patterned with a smaller width through a trim process, allowing for self-aligned formation of a pattern with a critical dimension smaller than the first mask pattern, and subsequent etching processes to achieve multiple patterning effects without the need for spacers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If conventional SADP approach is used to achieve smaller critical dimensions, then feature size is reduced, but uniformity of etching recessing deteriorates and spacer bending occurs

Engineering Contradiction:
Improvecritical dimensionVSAvoiduniformity of etching recessing
Core Design Contradiction:
Length of moving objectVSManufacturing precision

Solution Approach 1:

The patent extracts and removes the problematic spacer component from the conventional SADP process. By using a direct double patterning approach with two separate photoresist layers instead of spacers, the method eliminates spacer bending issues and etching recess loading non-uniformity while maintaining the ability to achieve smaller critical dimensions

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent segments the patterning process into two independent lithography-etch steps rather than using a single spacer-based process. The first photoresist layer defines initial patterns, and the second photoresist layer defines additional patterns, with each step being independently controllable to maintain uniformity and precision

Inventive Principle:
Principle #1Segmentation

2Length of moving object

If conventional SADP approach is used to achieve smaller critical dimensions, then feature size is reduced, but manufacturing yield deteriorates

Engineering Contradiction:
Improvecritical dimensionVSAvoidmanufacturing yield
Core Design Contradiction:
Length of moving objectVSReliability

Solution Approach 1:

By removing the spacer component from the process, the patent eliminates the sources of variability (spacer bending, non-uniform etching recesses) that directly impact manufacturing yield. The direct double patterning approach with two photoresist layers provides more consistent and predictable process outcomes

Inventive Principle:
Principle #2Taking out (Extraction)

3Length of moving object

If conventional SADP approach is used to achieve smaller critical dimensions, then feature size is reduced, but layout pattern transfer quality deteriorates

Engineering Contradiction:
Improvecritical dimensionVSAvoidlayout pattern transfer
Core Design Contradiction:
Length of moving objectVSManufacturing precision

Solution Approach 1:

The patent divides the pattern transfer into two separate lithography steps, each with its own photoresist layer and development process. This segmentation allows for better control of pattern transfer quality in each step, avoiding the cumulative errors that occur in the spacer-based conventional approach

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

By eliminating the spacer intermediate step, the patent removes the sources of pattern distortion and non-uniformity. The direct double patterning approach enables more faithful transfer of the intended layout pattern to the final structure

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS10460939B1Patterning method
Publication Date: 2019.10.29 UNITED MICROELECTRONICS CORP
  • US10460939B1 patent drawing
  • US10460939B1 patent drawing
  • US10460939B1 patent drawing

AI summary

A patterning method includes the following steps. A second mask layer is formed on a first mask layer. A patterning process is performed to the first mask layer and the second mask layer. The first mask layer is patterned to be a first mask pattern, and the second mask layer is patterned to be a second mask pattern formed on the first mask pattern. A first trim process is performed to the second mask pattern. A width of the second mask pattern is smaller than a width of the first mask pattern after the first trim process. A cover layer is formed covering the first mask pattern and the second mask pattern after the first trim process, and an etching process is performed to the first mask pattern after the step of forming the cover layer.