Maskable Level Shifter Circuit for Memory Bitline Write Operations

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Solution Overview

Problem

Existing Physical Page Address (PPA) designs for bit writable logic require more die area, consume more power, and introduce additional gate delay due to the use of two separate level shifters and a NOR gate in the write path.

Innovation Solution

A maskable level shifter circuit that includes a level shifter configured to receive a mask signal, allowing it to remove power when active and pull the output to a predetermined state, reducing the number of logic stages and power consumption, and eliminating the NOR gate from the write path.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If two separate level shifters and a NOR gate are used in the write path, then bit writable logic functionality is achieved, but die area increases and power consumption increases

Engineering Contradiction:

Improvebit writable logic functionalityVSAvoiddie area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent combines the level shifting and masking functions into a single integrated level shifter circuit, eliminating the need for separate level shifters and NOR gates. This merging of functions reduces the overall circuit area while maintaining the bit writable logic functionality through the maskable level shifter that can operate in both level shifting and masking modes

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The level shifter circuit is designed with multi-functionality, serving both as a level shifter and as a masking circuit. The maskable level shifter can disable its level shifting function when a mask signal is active, effectively replacing the NOR gate masking function. This universal design reduces component count and die area while preserving all required functionalities

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If two separate level shifters and a NOR gate are used in the write path, then bit writable logic functionality is achieved, but power consumption increases

Engineering Contradiction:

Improvebit writable logic functionalityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

By merging the level shifting and masking functions into a single circuit, the patent reduces the total number of active components. Fewer components mean fewer transistors switching, which directly reduces dynamic power consumption while maintaining the required bit writable logic functionality

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent extracts and eliminates the NOR gate from the write path by incorporating masking functionality directly into the level shifter. This removal of the separate masking component reduces the critical path length and the number of switching events, thereby reducing power consumption while preserving the masking function

Inventive Principle:

Principle #2Taking out (Extraction)

3Reliability

If two separate level shifters and a NOR gate are used in the write path, then bit writable logic functionality is achieved, but gate delay increases

Engineering Contradiction:

Improvebit writable logic functionalityVSAvoidgate delay

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent merges multiple logic stages into a single level shifter circuit with integrated masking capability. This consolidation reduces the number of sequential gate delays in the write path from five stages to three stages, as the level shifter performs both level shifting and masking functions without requiring separate NOR gate delays

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

By extracting and removing the NOR gate from the write path and incorporating its masking function directly into the level shifter, the patent eliminates an additional gate delay. This extraction of the separate masking function reduces the critical path length and minimizes the cumulative gate delay in the write operation

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS9875776B1Bit writability implementation for memories

Publication Date: 2018.01.23 QUALCOMM INC

AI summary

Maskable level shifter circuits and memories are provided. Memories may include a plurality of memory cells and a bitline coupled to the plurality of memory cells. The memories includes a maskable level shifter configured to receive write data and a mask signal. A maskable level shifter includes a level shifter configured to level shift the write data and output the level shifted write data to the bitline when the mask signal is inactive and a masking circuit configured to remove power from the level shifter when the mask signal is active. Another maskable level shifter includes a level shifter configured to level shift the write data and output the level shifted write data to the bitline when the mask signal is inactive and a masking circuit configured to output a predetermined state to the bitline when the mask signal is active.