Masked Atomic Bit Updates for Concurrent Shared Memory Access
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Solution Overview
Problem
Conventional atomic operations, such as CMPXCHG, prevent access to entire data storage locations, leading to unnecessary delays and computational overhead when only a subset of data bits are involved, while lock-based mechanisms introduce performance degradation and deadlock risks.
Innovation Solution
The masked atomic update instruction (CMPXCHGM) performs compare and exchange operations on select bits of a data structure, allowing masked access to prevent interference only on specified bits, enabling atomicity with granular control over data access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional atomic operations (CMPXCHG) are used to ensure data integrity, then data integrity is maintained, but access to entire data storage locations is blocked causing unnecessary delays and computational overhead
Solution Approach 1:
The patent segments the data storage location into individual bits and applies atomic operation masking to lock only the specific bits being modified. This allows other bits in the same data storage location to remain accessible to other threads, eliminating the unnecessary blocking of entire data locations that occurs with conventional atomic operations.
Solution Approach 2:
The patent implements local quality by applying different access permissions to different bits within the same data storage location. The mask parameter enables fine-grained control where only the relevant bits are protected with atomic operation semantics, while other bits maintain normal access patterns, optimizing both reliability and performance.
2Reliability
If conventional atomic operations (CMPXCHG) are used to prevent race conditions, then race conditions are avoided, but computational overhead increases due to blocking entire data storage locations
Solution Approach 1:
The patent segments the atomic operation scope from the entire data storage location down to individual bits through the use of a mask parameter. This segmentation reduces the computational overhead by minimizing the number of bits that need to be locked and processed atomically, while still maintaining race condition prevention for the relevant bits.
Solution Approach 2:
The patent applies partial action by performing atomic operations only on the necessary subset of bits rather than the entire data storage location. The mask parameter enables this partial action by specifying exactly which bits require atomic protection, reducing unnecessary computational work on unrelated bits.
3Ease of operation
If lock-based mechanisms are used for synchronization, then access control is achieved, but performance degradation and deadlock risks increase
Solution Approach 1:
The patent segments the critical section from the entire data storage location to only the specific bits that need synchronization. By using bit-level masking, the system achieves access control with minimal scope, reducing the likelihood of deadlocks and improving overall system performance while maintaining proper synchronization semantics.
Solution Approach 2:
The patent introduces a mask parameter that dynamically changes the scope of atomic operations based on the specific bits being accessed. This parameter-driven approach enables flexible access control that adapts to different synchronization needs, improving performance by reducing over-synchronization while maintaining ease of operation through a unified interface.
Data Source
AI summary
A masked atomic update instruction is described that atomically performs compare and exchange operations on select bits of a data structure. Executing the masked atomic update instruction compares respective source values with respective values of bits stored at a destination data storage location. If the respective bit values match, one or more of the respective bit values at the destination are replaced with one or more defined replacement values. Alternatively, if the respective bit values do not match, the destination is not modified. The masked atomic update instruction enables a processing unit to mask out bits of the destination data storage location that are not involved in the comparison or update. The masked atomic update instruction thus provides bit-level granularity by which another thread is prevented from accessing bits of the destination data storage location. This bit-level granularity advantageously permits multiple threads to simultaneously access a common data storage location.