Masked Cryptographic Operations Using Arithmetic-Boolean Share Conversion

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Solution Overview

Problem

Existing cryptographic systems are vulnerable to side-channel attacks, and existing countermeasures like masking methods do not effectively extend to higher-order security and are difficult to implement in hardware, especially when dealing with prime moduli and glitches.

Innovation Solution

A cryptographic system employing arithmetic and Boolean sharing functions, including a first sharing processing unit for arithmetic sharing, a second sharing processing unit for Boolean sharing, and a computation processing unit for recursive carry computation, to generate protected data blocks using arithmetic and Boolean share components, ensuring resistance against side-channel attacks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If arithmetic and Boolean conversion methods are extended to higher-order security, then security against side-channel attacks is improved, but device complexity increases

Engineering Contradiction:
Improvesecurity against side-channel attacksVSAvoidcomplexity of conversion methods
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the conversion process into separate arithmetic and Boolean sharing functions, processing different aspects of the data independently. The arithmetic sharing function handles numerical operations while the Boolean sharing function handles logical operations, allowing each to be optimized for its specific security requirements without overwhelming complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces random components as intermediaries between the arithmetic and Boolean sharing functions. These random components facilitate the conversion between different masking schemes while maintaining security properties, acting as a buffer that simplifies the overall conversion process.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If prime moduli are translated to hardware implementations, then cryptographic operations are improved, but resistance to glitches deteriorates

Engineering Contradiction:
Improvecryptographic operation efficiencyVSAvoidresistance to glitches
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary anti-action by incorporating glitch detection and prevention mechanisms into the hardware implementation before cryptographic operations execute. The system proactively identifies and mitigates potential glitches caused by prime modulus translations, preventing them from compromising security rather than reacting after damage occurs.

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The patent implements beforehand cushioning by adding redundancy and error correction capabilities to the hardware architecture. This cushioning layer absorbs the impact of glitches and faults, protecting the core cryptographic operations from being compromised by hardware imperfections or external interference.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS12634110B2Method and system for protecting cryptographic operations against side-channel attacks
Publication Date: 2026.05.19 SECURE IC
  • US12634110B2 patent drawing
  • US12634110B2 patent drawing
  • US12634110B2 patent drawing

AI summary

A cryptographic system for executing operations of a cryptographic scheme applied to encrypt a data block is provided. The cryptographic system comprises a first sharing processing unit configured to execute an arithmetic sharing function applied to the data block and providing as an output a first and a second arithmetic share component. The cryptographic system further comprises a second sharing processing unit and a computation processing unit. The second sharing processing unit is configured to determine a random component and to execute a Boolean sharing function applied to the first arithmetic share component and to the random component and providing as an output an intermediate Boolean share component. The computation processing unit is configured to execute a recursive carry computation function configured to compute a first, a second and a third Boolean share component from the second arithmetic share component, the random component and the intermediate Boolean share component.