Masked Data Processor Architecture Without Unmasking Operations

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Solution Overview

Problem

Current processors face challenges in reliably processing masked data without unmasking operations, which is essential for secure data handling in electronic systems.

Innovation Solution

A processor architecture that includes an arithmetic and logic unit, register banks, and masking circuits, allowing masked data to remain masked throughout processing, storage, and operations, using either arithmetic or logic masking types without converting to unmasked form.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If unmasking operations are implemented to process masked data, then data processing capability is improved, but security and reliability are worsened

Engineering Contradiction:
Improvedata processing capabilityVSAvoidsecurity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The processor is segmented into multiple specialized units: an arithmetic and logic unit for computations, an address generating unit for memory access, and separate register banks for data and masks. This segmentation allows each unit to handle masked data appropriately without requiring unmasking operations, thus maintaining security while enabling processing.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A masking circuit is introduced as an intermediary component that modifies the masking type of masked data during processing. This intermediary enables the system to handle different masking types (arithmetic and logic masking) without unmasking the data, resolving the contradiction between processing capability and security.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If masking type modification is implemented through masking circuits, then versatility in handling masked data is improved, but device complexity is worsened

Engineering Contradiction:
Improvemasking type handling capabilityVSAvoidprocessor architecture complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The masking circuit is designed with multi-functionality to handle both arithmetic masking type modification and logic masking type modification within a single component. This universality provides versatility in handling different masking types while minimizing the increase in device complexity by consolidating functions.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The masking circuit performs preliminary action by pre-modifying the masking type of data before it enters the arithmetic and logic unit or address generating unit. This preliminary preparation ensures that subsequent processing units receive data in the appropriate masking format, enabling versatile handling without requiring complex real-time conversion mechanisms throughout the processor.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If masked data is stored in register banks with separate mask registers, then data security is improved, but device complexity is worsened

Engineering Contradiction:
Improvedata securityVSAvoidregister bank structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The register bank is segmented into two distinct components: a data register for storing masked data and a separate mask register for storing the corresponding masking information. This segmentation enhances security by physically separating data from its mask, preventing unauthorized access to the original data while maintaining the structured organization needed for efficient processing.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20210109711A1Processor and method for processing mask data
Publication Date: 2021.04.15 STMICROELECTRONICS (GRENOBLE 2) SAS
  • US20210109711A1 patent drawing
  • US20210109711A1 patent drawing
  • US20210109711A1 patent drawing

AI summary

An embodiment relates to a method for processing masked data using a processor comprising an arithmetic and logic unit, in which the masked data remain masked during their processing in the arithmetic and logic unit.