Masked OR Zero Detection Circuit for Low-Power IC Security
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Solution Overview
Problem
Probing or forcing attacks on integrated circuits (ICs) pose a significant threat to security-critical electronic devices, and existing protection methods, such as masking techniques, often increase power consumption and add complexity to critical signal paths, making them inefficient for protecting zero detection logic.
Innovation Solution
A zero detection circuit utilizing a chain of masked OR circuits, where each masked OR circuit has data inputs, input masking bits, and an output masking bit, with inputs masked using XOR operations and adder-modulo-2 logic to generate a masked OR combination, effectively protecting zero detection logic without significantly increasing power consumption or complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If masking techniques are applied to protect zero detection logic, then security against probing attacks is improved, but power consumption increases and device complexity increases
Solution Approach 1:
The zero detection logic is segmented into multiple masked OR circuits arranged in a tree structure. Each circuit processes a subset of input bits with its own masking, dividing the protection task across multiple units rather than applying heavy masking to a single circuit, thereby distributing power consumption across segments.
Solution Approach 2:
The patent changes the masking parameter from full-strength masking applied uniformly to all zero detection circuits to selective masking where only certain OR circuits in the tree are masked based on their position and input significance. This parameter change reduces overall power consumption while maintaining security for critical detection paths.
2Reliability
If masking techniques are applied to protect zero detection logic, then security against probing attacks is improved, but device complexity increases
Solution Approach 1:
The zero detection function is segmented into a tree of OR circuits where only specific nodes are masked. This segmentation allows complexity to be concentrated in strategic locations rather than distributed throughout the entire detection logic, reducing overall hardware complexity while maintaining security.
Solution Approach 2:
The masked OR circuits serve multiple functions: they perform the logical OR operation for zero detection, apply masking for security, and propagate masked results through the tree structure. This multi-functionality reduces the need for separate protection circuits, thereby reducing overall device complexity.
3Reliability
If existing masking techniques are used, then protection against probing attacks is achieved, but the critical signal path becomes more complex and less efficient
Solution Approach 1:
Instead of masking the entire zero detection signal path from input to output, the patent inverts the approach by masking only specific intermediate nodes in the OR tree and leaving other paths unmasked or lightly masked. This inversion maintains protection while preserving signal path efficiency for non-critical paths.
Solution Approach 2:
Different regions of the zero detection circuit are assigned different masking strengths based on their security importance. Critical nodes in the OR tree receive strong masking, while less critical paths use weaker or no masking, optimizing the balance between protection and signal path efficiency through local quality differentiation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution efficiently protects zero detection logic by masking inputs and outputs, reducing the effort required to detect zero values while minimizing power consumption and additional hardware complexity, thus enhancing security against probing attacks.
Implementation Method 1
Each masked OR circuit is configured to output a bit equal to an OR combination, masked with the output masking bit, of the data input bits, each demasked with an input masking bit of the one or more input masking bits
Data Source
AI summary
A zero detection circuit includes a chain of masked OR circuits. Each masked OR circuit includes data inputs. Each data input is configured to receive a respective data input bit. Each masked OR circuit further includes an input mask input to receive one or more input masking bits, an output mask input to receive an output masking bit and a data output. The zero detection circuit is configured to output a bit equal to an OR combination, masked with the output masking bit, of the data input bits, each demasked with an input masking bit of the one or more input masking bits. One of the inputs of each masked OR circuit except the first masked OR circuit of the chain of masked OR circuits is coupled to the data output of the masked OR circuit preceding the masked OR circuit in the chain of masked OR circuits.