Masked PIM Scheduling Around Per-Bank DRAM Refresh
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Solution Overview
Problem
Conventional DRAM controllers execute single memory bank operations, such as per-bank refreshes, which limit the time available for all-bank PIM operations, reducing the practical use of processing-in-memory devices, especially in high-density systems.
Innovation Solution
Transform all-bank PIM operations into multiple masked PIM operations using a dynamic PIM operation scheduler that detects intervening per-bank commands, such as per-bank refreshes, and schedules masked PIM operations to avoid conflicts, thereby optimizing PIM throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DRAM controllers execute single memory bank operations (per-bank refreshes), then memory reliability is maintained through proper refresh, but the time available for all-bank PIM operations is reduced
Solution Approach 1:
The patent segments all-bank PIM operations into multiple masked PIM operations, where each operation targets a specific subset of memory banks rather than all banks simultaneously. This allows the memory controller to interleave refresh operations with PIM operations across different bank groups, maintaining refresh reliability while improving overall PIM throughput by utilizing previously idle banks.
Solution Approach 2:
The patent implements dynamic scheduling that adapts the masking pattern and timing of PIM operations based on the refresh schedule and bank availability. The controller dynamically adjusts which banks are masked and when PIM operations are issued, optimizing the balance between refresh requirements and PIM computational throughput in real-time.
2Productivity
If all-bank PIM operations are executed, then processing throughput is maximized, but conflicts with per-bank refresh commands occur
Solution Approach 1:
By dividing the memory banks into multiple groups and applying masking to specific groups during PIM operations, the patent enables refresh operations to proceed on non-masked banks without conflict. This segmentation allows simultaneous execution of refresh and PIM operations on different bank subsets, eliminating conflicts while maintaining high throughput.
Solution Approach 2:
The patent introduces a masking mechanism as an intermediary layer between the PIM operation requests and the physical memory banks. This masking layer mediates conflicts by selectively enabling or disabling access to specific banks, allowing the system to harmonize refresh requirements with PIM computational demands without compromising either.
3Productivity
If masked PIM operations are used to avoid refresh conflicts, then PIM device utilization is enhanced, but operation complexity increases
Solution Approach 1:
The patent designs the masking mechanism to serve multiple functions: it enables conflict avoidance with refresh operations, facilitates dynamic scheduling flexibility, and maintains backward compatibility with traditional memory operations. This multi-functionality reduces the need for separate complex control logic by consolidating multiple control objectives into a unified masking framework.
Solution Approach 2:
The patent controls operational complexity by dynamically adjusting masking parameters (which banks are masked and when) based on the refresh schedule and PIM workload characteristics. Rather than implementing a fixed complex scheduling algorithm, the system changes masking parameters adaptively, simplifying the control logic while achieving high utilization.
Data Source
AI summary
A system includes memory hardware including a memory and a processing-in-memory component. A system includes a host including at least one core. A system includes a memory controller including a scheduling system. The scheduling system transforms an all-bank processing-in-memory command into multiple masked processing-in-memory commands. The scheduling system also schedules the multiple masked processing-in-memory commands to the processing-in-memory component.