Masked Rejection Sampling Circuit for Side-Channel-Safe Key Generation
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Solution Overview
Problem
Current cryptographic systems like RSA and ECC are vulnerable to attacks by quantum computers, and key generation processes in lattice-based cryptosystems like Dilithium require protection against side-channel attacks.
Innovation Solution
A security device with a sampler circuit, bit string rejector circuit, and controller circuit performs rejection sampling and modular reduction using masked Boolean arithmetic, allowing parallel processing of small values to protect against side-channel attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If rejection sampling is performed with masking countermeasures to protect against side-channel attacks, then security against side-channel attacks is improved, but computational complexity and processing time increase
Solution Approach 1:
The rejection sampling process is segmented into multiple iterations where a predefined number of bit strings are processed in parallel. The sampler circuit generates multiple bit strings, and the bit string rejector circuit evaluates them simultaneously using masked Boolean arithmetic, dividing the computational burden across parallel operations rather than sequential processing.
Solution Approach 2:
The controller circuit pre-determines the number of bit strings to be processed in parallel before execution. This preliminary action allows the system to optimize the balance between security and efficiency by fixing the iteration count in advance, avoiding dynamic decision-making that would increase computational complexity during the actual sampling process.
2Reliability
If masking countermeasures are applied during rejection sampling and modular reduction, then protection against side-channel attacks is improved, but processing speed decreases
Solution Approach 1:
The sampler circuit, bit string rejector circuit, and modular reducer circuit are merged into a single integrated security device that processes multiple bit strings in parallel. By combining these functions in one device with shared masking infrastructure, the system achieves both security and efficiency that would be difficult to obtain with separate sequential processing units.
Solution Approach 2:
The system uses periodic action by processing a fixed number of bit strings in each iteration through the controller circuit. This periodic structure allows the masking operations to be optimized for regular, predictable execution patterns, improving processing speed while maintaining security against side-channel attacks that exploit irregular timing.
3Productivity
If multiple bit strings are processed in parallel iterations, then efficiency of random integer generation is improved, but device complexity increases
Solution Approach 1:
The system transitions from sequential processing to parallel processing by adding the dimension of multiple simultaneous iterations. The sampler circuit generates multiple bit strings that are evaluated in parallel by the bit string rejector circuit, achieving efficiency gains through dimensional expansion rather than increasing the complexity of individual processing steps.
Data Source
AI summary
A security device comprise a sampler configured to, in each iteration of a sequence of iterations, sample a string of n bits, a bit string rejector configured to reject the string of n bits in reaction to an AND combiner generating an AND combination of the sampled bits which is equal to 1, in case a given limit or an integer multiple of the given limit is equal to 2n−1, and AND-OR combiner generating an AND combination of the most significant bit of the sampled bits with an OR combination of the other bits of the sampled bits which is equal to 1 in case the given limit is equal to 2n−1+1; and a controller configured stop the sequence of iterations in reaction to a number of strings of n bits which have not been rejected being equal or above a predefined number of bit strings.