Masked Vector Comparison for Variable Length Decoding

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Solution Overview

Problem

Existing processor architectures face inefficiencies in performing variable length decoding due to the difficulty in vectorizing the process, leading to high memory overhead and cycle counts.

Innovation Solution

The introduction of a masked-vector-comparison instruction that allows for multiple comparisons between a source vector operand and a comparison target operand, with masking applied to consider variable symbol lengths, reducing the need for expanded lookup tables and improving processing throughput.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If variable length decoding is performed using existing processor architectures, then decoding functionality is provided, but memory overhead and cycle counts are high

Engineering Contradiction:
Improveprocessing throughputVSAvoidmemory overhead
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent segments the decoding process into parallel vector operations. Multiple codebook entries are loaded into vector registers and processed simultaneously through vectorized comparison operations, dividing the sequential decoding task into parallel segments that can be executed concurrently, thereby reducing memory overhead and improving throughput

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the operational parameters by introducing a mask value that specifies patterns of compared and non-compared bits. This allows the comparison operation to selectively ignore certain bits based on variable symbol lengths, enabling efficient variable length decoding without requiring expanded lookup tables for all possible length combinations

Inventive Principle:
Principle #35Parameter changes

2Productivity

If variable length decoding is performed using existing processor architectures, then decoding functionality is provided, but cycle counts are high

Engineering Contradiction:
Improveprocessing throughputVSAvoidcycle counts
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent segments the decoding process into parallel vector operations. Multiple codebook entries are loaded into vector registers and processed simultaneously through vectorized comparison operations, dividing the sequential decoding task into parallel segments that can be executed concurrently, thereby reducing memory overhead and improving throughput

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by pre-loading multiple codebook entries into vector registers before the actual decoding comparison. This preparation allows the subsequent vectorized comparison operations to proceed without repeated memory access delays, reducing cycle counts for the critical decoding path

Inventive Principle:
Principle #10Preliminary action

3Productivity

If masked-vector-comparison instruction is implemented, then processing throughput is improved, but instruction complexity increases

Engineering Contradiction:
Improveprocessing throughputVSAvoidinstruction complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges multiple operations into a single masked-vector-comparison instruction. The instruction combines vectorized comparison logic with mask application and result generation in one unified operation, allowing the processor to perform what would traditionally require multiple separate instructions in a single cycle, thus improving throughput while managing instruction complexity through consolidation

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12277420B2Masked-vector-comparison instruction
Publication Date: 2025.04.15 ARM LTD
  • US12277420B2 patent drawing
  • US12277420B2 patent drawing
  • US12277420B2 patent drawing

AI summary

A masked-vector-comparison instruction specifies a source vector operand comprising a plurality of source data elements, a mask value, and a comparison target operand. In response to the masked-vector-comparison instruction, an instruction decoder 10 controls processing circuitry 16 to: for each active source data element of the source vector operand, determine whether the active source data element satisfies a comparison condition, based on a masked comparison between one or more compared bits of the active source data element and one or more compared bits of the comparison target operand, the mask value specifying a pattern of compared bits and non-compared bits within the comparison target operand and the active source data element; and generate a result value indicative of which of the source data elements of the source vector operand, if any, is an active source data element satisfying the comparison condition. This instruction is useful for variable length decoding operations.