ECC Memory Pipeline for Consecutive Write Mask Operations
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Solution Overview
Problem
Semiconductor memory devices face increased susceptibility to soft errors due to reduced charge storage margins and leakage currents, leading to random single bit errors, which can be exacerbated by the use of error correction codes that increase operational time and reduce performance.
Innovation Solution
The implementation of a memory system with a write driver, data sense amplifier, error control code circuit, and control circuit that enables pipelining of consecutive write mask operations, allowing for concurrent execution of operations and reduced execution time by starting the second write mask operation before the first completes, thereby improving data integrity and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction code (ECC) is used with the memory, then data integrity is improved, but the time required for memory operations increases
Solution Approach 1:
The patent applies preliminary action by performing ECC encoding in parallel with memory write operations. The ECC circuit generates correction codes while data is being written to memory, so that when data is read, the correction codes are already available, eliminating the need to wait for ECC processing after read operations.
Solution Approach 2:
The patent implements continuity of useful action by maintaining parallel processing streams where ECC encoding, data writing, and subsequent read operations occur concurrently rather than sequentially. This allows the system to continuously perform useful work (ECC processing and memory operations) simultaneously, reducing total operation time while maintaining data integrity.
2Quantity of substance
If feature sizes of semiconductor memory are reduced, then memory capacity and area efficiency are improved, but the margin of error for detecting data state decreases
Solution Approach 1:
The patent applies beforehand cushioning by implementing ECC that can detect and correct errors before they propagate. The error correction codes provide a buffer against soft errors that become more likely with reduced cell sizes, cushioning the system against the increased vulnerability to charge leakage and alpha particle interactions.
3Use of energy by moving object
If voltage levels provided to semiconductor memory are reduced, then power consumption is limited, but the charge stored in each memory cell is reduced
Solution Approach 1:
The patent applies beforehand cushioning by using ECC to protect against errors caused by reduced charge storage. The error correction codes provide a safety margin that compensates for the lower charge levels in reduced-voltage operation, allowing the system to maintain reliability despite operating with smaller voltage swings and reduced stored charge.
Data Source
AI summary
Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.